Zenith Electronics Corporation

Gregg Chandler

Babu Rajaram

Conventional bit-mapped address locations in a character oriented video random access memory (RAM) in which each character is represented by a bit mapping array comprised of ten lines each including eight pixels, or eight bits of information, in an X-Y matrix address organization are redefined in terms of the character and row address locations of a graphics oriented cathode ray tube controller for driving a video display. Groups of bits in the X-Y matrix address locations of the video RAM are shifted in a predetermined manner in generating a redefined, 1:1 mapping function addressing code which is provided to a cathode ray tube controller for driving the video display. A video RAM mapping module is provided for reorganizing the video RAM addresses and translating these addresses throughout the page of the video RAM in providing more efficient graphics mapping while retaining high resolution alphanumeric character video resolution. In one embodiment, a video display start bit is incremented by an 8-bit adder to provide for scrolling on a line-by-line basis without moving character bytes from one location to another in the video RAM.

Growing community of inventors

St. Joseph, MI, United States of America

Gregg Chandler