Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Gregg Bernard Lesartre

Gary Belgrave Gostin

Derek Alan Sherlock

Russ William Herrell

Martin Foltin

John William Bockhaus

Harvey Ray

Dale Calvin Morris

Craig William Warner

Gregory L Ranson

Darel N Emmot

Andrew Ray Wheeler

Jonathan P Lotz

Chris Michael Brueggen

Naveen Muralimanohar

Blaine Douglas Gaither

Nicholas George McDonald

Paolo Faraboschi

Mark Edward Shaw

Yoocharn Jeon

Russell C Brockmann

Rajeev Balasubramonian

Ashok Kumar

Donald M Kipp

Doug Quarnstrom

Erik Ordentlich

Douglas Benson Hunt

Robert J Brooks

Patrick Knebel

Tyler J Johnson

Steven T Mangelsdorf

David Paul Hannum

Anthony M Ford

Joseph F Orth

Paul L Perez

Jishen Zhao

Greg Astfalk

Michael Joseph Phelps

Vipul Gandhi

Brendan A Voge

David Jerome Johnson

Norell Estella Menhusen

Brian S Birk

Richard Stanley Williams

Samuel D Naffziger

Joseph Foster

Gary A Gibson

Douglas L Voigt

Siamak Tavallaei

Robert S Schreiber

Brent Buchanan

James M Mann

Lidia Warnes

Richard H Henze

David Plaquin

Alan Lynn Davis

Kevin L Miller

Guy Lowell Kuntz

Andrew Hana

Paul Bouchier

Bryan Stephenson

Robert McFarland

Richard Dickert Powers

Gregory Keith Trezise

Craig Lawrence Warner

Christopher Michael Brueggen

Carey Huscroft

John M Wastlick

Peter David Maroni

Todd J Kjos

Brian Matthew Johnson

Jason Douglas Jung

James Donald Regan

Robert E Naas

Ryan Lee Weaver

Al Davis

James R Greener

Ryan Akkerman

Glen Edwards

John Kim

James D Gibson

Christopher P Woody

Leon Hong

Darel Nea Emmot

A packet-processing method includes looking up a first match-action table on a network interface card (NIC) for a received packet; in response to finding a matching entry indicating an action, queuing the received packet in a first queue and storing the action data in an instruction memory; and responsive to not finding a matching entry, queuing the received packet in the first queue and a second queue. The method includes selecting a first packet from the first queue for processing, which comprises performing a corresponding action stored in the instruction memory; selecting a second packet from the second queue for processing, which comprises forwarding a portion of the second packet to a processor, which looks up a second match-action table; and receiving, from the processor, a lookup result, thereby allowing a third packet in the first queue corresponding to the second packet to be processed based on the lookup result.

NIC line-rate hardware packet processing

Candidates for selection in a weighted arbitration system are assigned priority weights and random weights. The winning candidate is determined using a tree of selectors such as a comparators. At each stage of the tree, the candidate having the greatest priority weight is selected to pass to the next stage. If multiple candidates are tied for the greatest priority weight, the candidate having the greatest random weight is selected to pass to the next stage.

Arbiter with random tie breaking

A method comprises receiving a message comprising an identifier for an address template, using the identifier to select the address template from a set of address templates, determining a set of memory addresses for a corresponding set of memory operations using the address template, and executing the memory operations.

Remote memory access using memory address templates

Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.

Data management on memory modules

A communications device that includes a requester and a responder may support multiple transaction classes, including an ordered transaction class, while maintaining a bifurcated requester/responder architecture. Before a responder has a non-posted transaction response to transmit on an interconnect, it receives an indication from the requester that there is not a pending posted transaction on the interconnect.

Device supporting ordered and unordered transaction classes

One embodiment can provide an apparatus. The apparatus can include a persistent flush (PF) cache and a PF-tracking logic coupled to the PF cache. The PF-tracking logic is to: in response to receiving, from a media controller, an acknowledgment to a write request, determine whether the PF cache includes an entry corresponding to the media controller; in response to the PF cache not including the entry corresponding to the media controller, allocate an entry in the PF cache for the media controller; in response to receiving a persistence checkpoint, identify a media controller from a plurality of media controllers based on entries stored in the PF cache; issue a persistent flush request to the identified media controller to persist write requests received by the identified media controller; and remove an entry corresponding to the identified media controller from the PF cache subsequent to issuing the persistent flush request.

System and method for tracking persistent flushes

One embodiment of the present invention provides a switch. During operation, the switch maintains a first counter to indicate a first number of packets in a queue of the switch. The switch then determines whether a clock of the switch has reached a threshold value. If the clock reaches the threshold value, the switch starts maintaining a second counter to indicate a second number of packets in the queue that have been received after the clock has reached the threshold value. The switch continues to decrement the first counter in response to a packet leaving the queue until the first counter reaches a value of zero. When the clock reaches a maximum value supported by the clock, the switch drops a third number of packets from the queue indicated by the first counter.

Method and system for enhanced queue management in a switch

A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

Split mode addressing a persistent memory

A component group table in a receiving node of a computer network stores access permission information for enabling the receiving node to validate an access request issued by a requesting node. An incoming access request at a receiving node includes a subnet ID/component ID ('SID/CID') tuple. The receiving node selectively computes a component group table address for the requesting node according to an address mapping function determined by the value of at least one predetermined bit within the SID/CID tuple of the incoming access request. Using at least one bit in the SID/CID tuple enables the establishment of at least two address mapping regions in the component group table, such as separate regions for storage nodes and compute nodes in the network.

Utilization of component group tables in a computing network

A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

External memory controller

A device including a processor configured to access data to execute multiple instructions and a first cache coupled to the processor, are provided. The first cache is configured to hold a first data fetched from a memory by a first instruction that has been retired. The device also includes a side cache coupled to the first cache and to the processor, the side cache configured to hold a second data fetched from the memory by a second instruction, wherein the second instruction has not been retired from the processor. And the device includes a cache management unit configured to move the second data from the side cache to the first cache when the second instruction is retired, the cache management unit further configured to discard the second data when it is determined that the second instruction is abandoned.

Side cache

A method for restricting write access to a non-volatile memory. The method includes receiving a request to write to a protected location in the non-volatile memory and determining whether the protected location is in a write-protected state. If the protected location is not in a write-protected state, the method includes writing data indicated by the request to the protected location. If the protected location is in a write-protected state, the method includes rejecting the request. The protected location stores a validation key to validate the contents of another portion of the non-volatile memory.

Systems and methods for restricting write access to non-volatile memory

According to an example, a lock may be requested by a first redundancy controller from a parity media controller to perform a first sequence that accesses multiple memory modules in a stripe. The lock may be acquired for the stripe so that the first sequence may be performed on the stripe. The lock may then be released from the stripe.

Serializing access to fault tolerant memory

In various examples, a device comprises a memory. The memory comprises a plurality of dies and logic. The logic may: determine a tolerable bit error rate (BER) of the memory based on whether one of the plurality of dies has failed, and adjust a parameter of the memory based on the tolerable BER.

Adjusting memory parameters

Growing community of inventors

Fort Collins, CO, United States of America

Gregg Bernard Lesartre