Hewlett-Packard Company

Greg Woods

Robert Campbell

Carol Elise Bassett

A control unit is assigned to each microprocessor of a multiprocessor (MP) system. Each control unit is in communication with its associated microprocessor and the system bus. Each control unit comprises a register set having bit registers and word registers. Messages can be sent to one or more of the microprocessors concurrently via a select function. Specifically, a data byte is bit sliced or bit masked so that the select register associated with one or more processors is activated. The bit registers which are activated, enable associated word registers for subsequent accesses. Consequently, one or more processors may be accessed concurrently. Moreover, bit pause registers are utilized so as to simultaneously pause one or more processors. Finally, bit identification registers may be read by any processor to determine the location of the processor.

System for employing select, pause, and identification registers to

A redirector in either software or hardware can is used to distribute global interrupts among all processors of a multiprocessor (MP) system, which may have multiple architecturally-isolated buses. When redirecting interrupts using software, a default processor receives all interrupts and redirects them to destination processors. When redirecting interrupts using hardware, a discrete redirector in hardware forwards all interrupts to particular processors based on a routing, or look-up, table. Another implementation incorporates interrupt snooping with either software or hardware interrupt redirection where interrupt response is critical for I/O cards.

Redirection of interrupts to microprocessors

A memory property tagging apparatus is interfaced with one or more caches which are associated with one or more microprocessors of a multiprocessor system having shared memory and a bus network. The apparatus masks off any snoop cycles on the bus network if data corresponding to an address is exclusive to its associated microprocessor(s). The apparatus can specify to its associated one or more caches whether data is cacheable or not. The apparatus can specify to its associated one or more caches whether data is to be treated as write-through or write-back. Finally, the apparatus can translate preselected memory addresses on the bus network into input/output (IO) addresses.

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San Jose, CA, United States of America

Greg Woods