Sun Microsystems, Inc.

Greg Williams

Leslie Dean Kohn

Dale Robert Greenley

Ming Yeh

Robert Yung

Huoy-Ming Yeh

A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array.

Hit bit for indicating whether load buffer entries will hit a cache when

A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array. A method and apparatus allow access to the first level cache and second level cache to occur simultaneously for two separate LOADs in the load buffer.

Methods and apparatuses for servicing load instructions

In a processor, an instruction unit that issues a plurality of instructions is coupled to a mapping unit. Each instruction contains at least one 'virtual' address corresponding to a user-addressable register as defined by an instruction set architecture. A register file having a number of physical register addresses in excess of the user addressable virtual register address is also coupled to the mapping unit. The mapping unit receives instructions from the instruction unit and generates a map value for each virtual register address. The mapping unit also maintains a status value for each physical register address. Maintaining the status value provides for out-of-order completion and in-order retirement. A new mapping is generated each time a virtual register address is used as a destination register address of an instruction. This insures that no physical register address will be overwritten before all older instructions have been resolved. This, in turn, provides for precise exception handling, which is accomplished by unwinding the instruction sequence from the youngest to the oldest instruction up to the point where the exception occurred.

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Palo Alto, CA, United States of America

Greg Williams