Vitesse Semiconductor Corporation

Greg Warwar

Tim Coe

Data receivers often include equalizers for operating on received signals. The equalizers often have a plurality of taps, with signals from each tap weighted based on tap settings or values. The tap settings may be set based on bit error rates of data output from the equalizer. In some embodiments data output from the equalizer is split into two signals, and the two signals are processed to indicate a data eye of the data output from the equalizer. Preferred tap settings may be determined by setting tap settings to different values and using tap settings expected to maximize the data eye. This may be performed separately for different bit settings in an attempt to reduce effects of inter-signal interference.

Adaptive data recovery system with input signal equalization

A clock recovery unit is used to recover a clock signal from a transmitted data signal. The clock recovery unit includes a phase locked loop (PLL) circuit and a frequency detection circuit. The frequency detection circuit includes a digital phase tracking circuit (DPTC), which uses a rotational phase shifter to shift phase of a variable clock signal from a voltage controlled oscillator in the PLL circuit, in discrete amounts from 0 to 360 degrees, depending on a digital input code provided by a digital accumulator, which receives up or down count signals from a phase comparator. The shifted variable clock signal is provided to a phase/frequency detector, which provides an output to a glitch suppressor to suppress small phase differences prior to providing the output to the PLL circuit. When the frequency difference between the variable clock signal and the reference clock signal is large, the phase/frequency detector drives the frequency in the correct direction. When the frequency difference is small, the DPTC keeps the phase of the shifted variable clock signal aligned to the phase of the reference clock signal.

Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal

A high bandwidth clock buffer, including a steering circuit, significantly increases the maximum frequency at which CMOS technology can be used to perform high-speed logic functions. In particular, the clock buffer includes a steering circuit for enhancing a voltage follower stage. The steering circuit includes steering transistors positioned between voltage follower transistors and constant current sources. The steering circuit switches all or substantially all of the current from both of the constant current sources through whichever of the two voltage follower transistors is being pulled low, thus doubling the amount of current that is available for slewing when the output is being pulled low. At the same time, since the voltage follower transistor that is being pulled high no longer has to source the constant current I , the effective maximum current that can be supplied to charge up the load capacitance is increased by approximately I . The clock buffer provides a higher unity gain bandwidth than a standard CML buffer, while maintaining a well controlled delay which will track other logic gates.

High bandwidth clock buffer

Phase selection circuit for selecting a phase from signal source generating a multi-phase clock signal is implemented utilizing a single stage of multiplexing gates for receiving taps from signal source, thus minimizing mismatch between phases. Multiplexing gates, connected together at their outputs, select between a tap and an inverse tap and are always left on. The outputs from multiplexing gates are analog summed together to create a single phase output signal which may be shifted in phase by one tap simply by inverting one of the input taps to a multiplexing gate, thus reducing glitching at output signal. Phase interpolation is provided for by further phase shifting the output in steps smaller than one tap utilizing multiplexor circuit which interpolates in multiple steps between a tap and inverse tap. Phase selection circuit provides for provides maximum bandwidth capability, while minimizing mismatch and glitching.

Phase selection circuit

A single-gate SCFL delay cell is disclosed for implementation in a common ring oscillator VCO. The delay cell has a differential input stage the output current from which is fixed by two resistors. The differential input stage drives a source follower output stage providing an output capable of driving the differential input of the next stage of the oscillator. The current sources typically used in the source follower output stage have been replaced by voltage-to-current converters. The voltage-to-current converters are comprised of two MESFET devices the gates of which are coupled to a differential control voltage. The source of each of the two devices is coupled to a current source the value of the two current sources being equal. The resistor couples the two sources together such that the voltage drop across the resistor governs how much current is conducted by each of the two devices. The drain of one of the devices is coupled to the supply while the drain of the other device is coupled to the source of the source follower output stage. Thus, the output current of the source follower will be dictated by the difference between the voltage drop across the resistor.

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Santa Paula, CA, United States of America

Greg Warwar