Cray Research, Inc.

Silicon Graphics, Incorporated

Greg Thorson

Randal Steven Passint

Michael Brian Galles

Mark S Birrittella

Steven M Oberlin

Richard E Kessler

Steven Lee Scott

A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4&times;8&times;4 torus topology.

Hybrid hypercube/torus architecture

A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving messages, output ports for sending messages from the router, two types of virtual channels, a lookup table associated with the input port having a lookup table virtual channel number, and a virtual channel assignment mechanism. The virtual channel assignment mechanism assigns an output next virtual channel number for determining the type of virtual channel to be used for routing from a next router along a given route. The next virtual channel number is assigned based on the lookup table virtual channel number and an input next virtual channel number received from a previous router along the given route.

Virtual channel assignment in large torus systems

Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping synchronization partitions are available simultaneously through the use of a plurality of parallel synchronization contexts. The present synchronization mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes. The present barrier/eureka mechanism also supports zero to N processor entities at each router node ('leaves' on the barrier tree), and provides a barrier sequence counter for each barrier context in order to resolve potential race conflicts that might otherwise arise.

Seralized race-free virtual barrier network

A multiprocessor computer system includes processing element nodes interconnected by physical communication links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions. The directions from the local table are selected for routing from the next router along a given route if the current processing element node is in a destination global partition or if the current processing element node is one plus or minus hop from reaching the destination global partition and the route is exiting on a port that routes to the destination global partition, else the directions from the global router table are selected for routing from the next router.

Router table lookup mechanism

A multidimensional interconnection and routing apparatus for a parallel processing computer connects together possessing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.

Networked multiprocessor system with global distributed memory and block

A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the processing elements with a host system. An interconnection network connects together the processing element nodes in an X, Y, and Z dimension. The network includes communication paths connecting each of the plurality of processing elements to adjacent processing elements in the plus and minus directions of each of the X, Y, and Z dimensions.

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Altoona, WI, United States of America

Greg Thorson