Advanced Micro Devices Corporation

Greg Smaus

Larry David Hewitt

Derrick R Meyer

Benjamin T Sander

Michael T Clark

David N Suggs

Michael A Filippo

In one illustrative embodiment, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit is adapted to initiate a table walk process to convert a virtual memory address to a physical address. The buffer is adapted to store pending memory access requests previously processed by the translation unit. The comparator is adapted to determine if a physical address generated by the table walk process of the translation unit conflicts with a physical address of at least one of the pending memory access requests, and deliver a control signal to the translation unit for canceling the table walk process in response to determining that a conflict exists.

Method and apparatus for maintaining coherency in a translation lookaside buffer

A multi-processor computer system includes at least a first and second processor coupled to a host bus. The first processor accesses a first set of registers using a first plurality of addresses over the host bus. A second processor accesses a second set of registers using the first plurality of addresses over the host bus. A first integrated circuit forms a bridge between the host bus and an input/output bus. The first integrated circuit receives access requests for the first and second sets of registers from the first and second processors, respectively. A second integrated circuit, coupled to the input/output bus, includes a first and a second local interrupt controller, the first and second sets of registers being part of the first and second local interrupt controllers. The first integrated circuit, responsive to an access request from one of the processors to one of the first plurality of addresses, outputs information on the input/output bus indicating the address of the register being accessed and which of the first and second processors made the access request, thereby specifying one of the first and second sets of registers.

Address space conversion to retain software compatibility in new architectures

A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.

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Austin, TX, United States of America

Greg Smaus