Nvidia Corporation

Greg Palmer

Lacky V Shah

Brian S Pharris

Jerome Francis Duluk, Jr

Jack H Choquette

Shirish C Gadre

John H Edmondson

Olivier Giroux

Ronny Krashinsky

Manan Patel

Luke Durant

Gentaro Hirota

Ravi Kiran Manyam

Ze Long

Jeff Tuckey

Prakash Bangalore Prabhakar

Wish Gandhi

Apoorv Parle

Rajballav Dash

Steve Heinrich

Sandeep Navada

Eric Werness

Naman Govil

Shayani Deb

Jonah Matthew Alben

Brian Matthew Fahs

Praveen Joginipally

Jonathon Evans

Phil Johnson

Kaushik Nadadhur

Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.

Virtualizing hardware processing resources in a processor

A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Cooperative group arrays

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

Distributed shared memory

Apparatuses, systems, and techniques to optimize processor resources at a user-defined level. In at least one embodiment, priority of one or more tasks are adjusted to prevent one or more other dependent tasks from entering an idle state due to lack of resources to consume.

User-defined metered priority queues

Growing community of inventors

Cedar Park, TX, United States of America

Greg Palmer