Lsi Logic Corporation

Greg Maturi

David R Auld

Gregg Dierke

Darren Duane Neuman

Anil Khubchandani

An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected. The proper frame interval can be determined from the information in the header following each valid synchronization code, or can be determined by counting the number of bits between the first and second valid synchronization codes. The decoder can be muted while out of synchronization to minimize distortion of the audio presentation.

Hysteretic synchronization system for MPEG audio frame decoder

A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list. A second interrupt is generated each time a data unit is decoded, and the host microcontroller responds by accessing the list using the starting address of the data unit to obtain the corresponding PTS, and thereby the desired decoding time. Decoding and presentation are synchronized by comparing the desired decoding time with a system clock time. If the desired decoding time is later than the system clock time by more than one presentation (frame) time period for the data unit, presentation of the data unit is skipped. If the desired decoding time is earlier than the system clock time by more than the presentation time period, presentation of the data unit is repeated.

MPEG decoding system adjusting the presentation in a predetermined

A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

MPEG audio synchronization system using subframe skip and repeat

A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

Serial clock synchronization circuit

A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. An input buffer arrangement includes first and second buffer memories which each have a capacity to store one subframe. The first and second buffer memories are used alternatingly, with one storing a subframe of input data while another subframe is being read out of the other. A third buffer memory, which has a capacity to store at least one subframe, is provided upstream of the first and second buffer memories to prevent the first and second buffer memories from overflowing or underflowing.

MPEG audio decoding system with subframe input buffering

A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list. A second interrupt is generated each time a data unit is decoded, and the host microcontroller responds by accessing the list using the starting address of the data unit to obtain the corresponding PTS and thereby the desired decoding time. Decoding and presentation are synchronized by comparing the desired decoding time with a system clock time. If the desired decoding time is later than the system clock time by more than one presentation (frame) time period for the data unit, presentation of the data unit is skipped. If the desired decoding time is earlier than the system clock time by more than the presentation time period, presentation of the data unit is repeated.

MPEG decoding system including tag list for associating presentation

A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a late point in time, samples are either repeated or dropped to correct any error in the bitstream signal.

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Tracy, CA, United States of America

Greg Maturi