Silicon Magic Corporation

Greg L Tanaka

Sean Hsi-an Kuo

Michael M Lee

Gregory Mitchell Stefanek

Kenneth Choy

Aspects for effectively improving the throughput in a rasterization pipeline for image rendering in a computer system are provided. A method aspect includes receiving data for a chosen number of pixels in a Z-test mechanism of the rasterization pipeline, performing Z-test determinations for the chosen number of pixels in a same clock cycle to achieve faster processing in the Z-test mechanism than other portions of the rasterization pipeline, and tagging the chosen number of pixels based upon the Z-test determinations to indicate pass/fail status for rendering. A circuit aspect includes at least one memory device for storing pixel data, a Z-test mechanism, the Z-test mechanism within the rasterization pipeline and coupled to the at least one memory device for determining a pass/fail rendering status for a plurality of pixels received in parallel from the at least one memory means, and a plurality of mechanisms forming a portion of the rasterization pipeline following the Z-test mechanism, the plurality of mechanisms for processing pixel data with a pass status sequentially.

Method and system for improved z-test during image rendering

Aspects for increasing efficiency of memory accesses during graphics rendering are provided. A preferred method aspect includes providing a plurality of memory banks for data, and decoding input signals that indicate accessing of at least one of the plurality of memory banks for a desired plurality of words of data. The method further includes splitting data access across the plurality of memory banks to allow parallel selection of an output from at least one of the plurality of memory banks as the desired plurality of words of the data, wherein latency of data access is amortized. A system aspect for improving data transfer from memory to a texture mapping unit includes a plurality of cache banks for storing texel data, a bank decode unit coupled to the plurality of cache banks for decoding a plurality of input signals indicative of selection of texel data from one or more of the plurality of banks, and selection control logic for receiving decoded address data from the bank decode unit and controlling selection of the plurality of cache banks to retrieve the texel data for output to the texture mapping unit.

Method and system for improved memory interface during image rendering

Apparatus, method, and system aspects for providing efficient accesses to memory in a computer system, the computer system including a controller, are described. Included in the aspects are a random access memory array having a plurality of rows and columns and coupled to the controller, and a column selection mechanism coupled to the memory array and the controller with the column selection mechanism being divided into predetermined portions for providing column selection signals to access chosen portions of a row in the memory array. Further included as the column selection mechanism is a multiplexer. In one embodiment, the multiplexer is divided into halves and provides separate selection signals for accessing upper word halves and lower word halves of the random access memory.

Growing community of inventors

Sunnyvale, CA, United States of America

Greg L Tanaka