Micron Technology Incorporated

Greg King

Brent Keeth

Troy A Manning

Brian L Johnson

David K Ovard

George Edward Pax

Roy Edgar Greeff

Ronnie M Harrison

Joo S Choi

Dragos Dimitriu

Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.

Tri-state driver circuits having automatic high-impedance enabling

Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

Phase interpolators and push-pull buffers

Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled to a common-mode pre-emphasis module, the center-swing signal generator to receive a low swing current mode logic (CML) signal and output a center-swing signal, and a full-swing cross-coupled inverter coupled to the center-swing signal generator, the full-swing cross-coupled inverter to receive the center-swing signal and output a full-rail single-ended swing signal. Additional apparatus, systems, and methods are disclosed.

Generating a full rail signal

Some embodiments include apparatus and methods having an output line, clock nodes to receive clock signals, the clock signals being out of phase with each other, and selector circuits to receive data in parallel. In at least one embodiment, the selector circuits are responsive to the clock signals to transfer the data serially to the output line. Such apparatus and methods can also include a control unit to influence a portion of a signal that represents at least a portion of the data at the output line. Additional apparatus and methods are described.

Data serializer apparatus and methods

A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

Method and system for generating reference voltages for signal receivers

Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of the invention receives two differential input signals and outputs a single output signal with low voltage transistors and programmable impedance and on-die termination circuits. The pseudo-differential output driver consumes little circuit area and has low output capacitance.

Growing community of inventors

Hastings, MN, United States of America

Greg King