Cypress Semiconductor Corporation

Greg J Richmond

Gabriel M Li

Babak A Taheri

Steve Whelan

Bihama Vedaste

John Chiong

Sangeeta Raman

Ahmet Akyildiz

Paula O'Sullivan

Dean Hamilton

Alex Shkidt

The present invention provides a means for efficiently and securely collecting, storing, and sharing all types of personal, electronic information from, for and between individuals and business users using software that runs on multiple personal, business and cloud computing systems. The information of a primary user is stored in an encrypted relational database which associates the private data with private data fields needed by secondary users or various business users. Each entity is assigned one unique user identity to ensure consistency in data privacy and sharing. Attributes for data groups exist to define the secondary users and business users who the primary user has authorized for access to or master sourcing of certified data. Change lists, including conditions for implementation, are created to facilitate management, scheduling and distribution of changes. Collection, storage, and distribution of personal data is assisted by robotic process automation algorithms.

Secure personal information database

A method for creating a map navigable by human means through unmapped areas including footpaths, small alleyways, structural and geographical barriers is disclosed. Mobile position recording devices including for example global navigation satellite system (GNSS) receivers, accelerometers, and magnetic orientation circuits plus monitoring software and means for data storage are provided to individuals who then travel to various destinations on foot and/or by mechanically assisted means. The position recording devices record route and location information with sufficient detail to provide a navigable map of the routes taken. The routes of various individuals are combined to provide an area wide map of navigable routes and repeated routes are identified and averaged over time to provide increased route detail and accuracy. The location and route data are separated into public and private data and the identity of the service recipient is protected from disclosure to service providers.

Method for secure and accurate mapping of locations and routes

An oscillator circuit is provided having an oscillating amplifier circuit connected to a resonator. The oscillator/amplifier and resonator are preferably fabricated on a single die using semiconductor fabrication tools. Included with the circuitry is a temperature sensor or transducer, an execution unit, non-volatile memory, a modulator, and frequency synthesizer, all of which are integrated together on the substrate, along with the piezoelectric crystal resonator. The frequency synthesizer can preferably include a phase-locked loop with a divider that is in a feedback loop of the phase-locked loop, in which a divide-by value is received from a modulator that achieves finer and higher resolution frequency selectivity from the voltage-controlled oscillator, also within the phase-locked loop, as an output from the crystal oscillator.

Resonator and amplifying oscillator circuit having a high resolution skew-compensated frequency synthesizer integrated on a single substrate

A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Circuit and method for monitoring the status of a clock signal

A phase shift apparatus, system and method are described herein for synchronizing output signals upon one or more components of a synchronous system. In one embodiment, the phase shift apparatus may be implemented as a clock generation circuit, which is configured to provide synchronous clocking signals to one or more components of the synchronous system. In another embodiment, the phase shift apparatus may be implemented as a data interface circuit, which is configured to provide error-free data transmission within a synchronous system. In either embodiment, the phase shift apparatus is configured to shift the plurality of signals by programmable first phase shift amounts prior to shifting the plurality of signals by programmable second phase shift amounts. As such, the phase shift apparatus is adapted to substantially eliminate clock skew, data skew and/or jitter, which may otherwise adversely affect the synchronous system. In addition, the phase shift apparatus is adapted to provide a phase resolution, which allows accurate control of such timing delays at substantially any operating frequency.

Apparatus, system, and method for synchronizing signals received by one or more system components

Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.

Circuit and method for monitoring the integrity of a power supply

A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

System and method for monitoring a power supply level

A buffer circuit, system, and method are provided. The buffer circuit includes a control circuit coupled to an output of the buffer, or possibly to an output of the first stage of a buffer. A pre-charge circuit is also provided coupled to bias an input of the control circuit to a voltage value approximately near a threshold voltage of the control circuit. The pre-charge bias amount is slightly less than the amount needed to place the control circuit in a high current conduction state. A coupling circuit is thereafter used and adapted to couple an input voltage applied to the buffer circuit to the input of the control circuit. This causes the control circuit to enter the high current conduction state. Depending on the input impedance of the coupling circuit, by pre-charging the coupling circuit input, less time is needed to cause the coupling circuit to enter and thereafter leave a high current conduction state. Therefore, by pre-charging the coupling circuit, output transitions from the buffer circuit can be accelerated and propagation delay reduced. The pre-charge circuit and the control circuit operate on one or more stages of a single or multi-stage buffer, operate on single-ended or differential/complementary input/output, and operate to speed up either the rising, falling, or both edges transitions at the output of the buffer.

Capacitive feedforward circuit, system, and method to reduce buffer propagation delay

An analog spread spectrum signal generation circuit. A clock generator generates a periodic signal. A plurality of switchable analog loading elements each load the periodic signal by a respective load to vary propagation delay of the periodic signal to an output node. A decoder controls the plurality of switchable analog loading elements. A counter coupled to drive the decoder causes the output node to generate a periodic spread spectrum signal with modulated phase. In one embodiment, the periodic spread spectrum signal with modulated phase is used for reducing radiated electromagnetic interference and downstream phase-locked loop tracking error.

Analog spread spectrum signal generation circuit

Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single ended seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.

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Sunnyvale, CA, United States of America

Greg J Richmond