Intersil Americas Inc.

Sarda Technologies, Inc.

Greg J Miller

Kun Xing

Bogdan M Duduman

William R Richards, Jr

John Kenneth Fogg

William E Batchelor

Anthony G P Marini

Michael M Walters

Shea Lynn Petricek

The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Gate driver for depletion-mode transistors

A voltage converter including a buck converter and a capacitive voltage divider. The converter includes four capacitors, a switch circuit, an inductor and a controller. A first capacitor is coupled between a reference node and a first output node which develops a first output voltage. A second capacitor is coupled between an input node and either the reference node or the first output node. The switch circuit couples a third capacitor between the reference and first output nodes in a first state of a PWM signal, and couples the third capacitor between the first output and input nodes in a second PWM signal state. The inductor is coupled to the third capacitor and provides a second output node coupled to the fourth capacitor providing a second output voltage. The controller controls the duty cycle of the PWM signal to regulate the second output voltage to a predetermined level.

Voltage converter with combined buck converter and capacitive voltage divider

A pulse control clock generator for a voltage regulator including a comparator, a window circuit, a filter circuit, a ramp circuit, and a current circuit. The comparator compares a ramp voltage with a compensation voltage and provides a corresponding pulse control signal. The compensation voltage is indicative of output voltage error. The window circuit adds a window voltage to the compensation voltage to provide a hysteretic voltage. The filter circuit filters the hysteretic voltage to provide a filtered hysteretic voltage, such that a difference between the compensation voltage and the filtered hysteretic voltage is reduced in response to a load increase. The ramp circuit provides a repetitive ramp voltage which ramps between the filtered hysteretic voltage and the compensation voltage based on the pulse control signal. The current circuit increases a slope of the ramp voltage in response to the load increase.

PWM clock generation system and method to improve transient response of a voltage regulator

A battery charging and power delivery system for a portable electronic device includes a first connection that connects the system to an AC/DC power adaptor. A second connection connects the system to the power bus of the portable electronic device. A third connection connects the system to a battery. A capacitor voltage divider circuit provides power to the system power bus through the second connection and provides power through the third connection. A controller provides control signals to the capacitor voltage divider and to the AC to DC power adaptor.

System and method of charging a battery and power delivery using an adapter and capacitor voltage divider

A power switching stage architecture for a buck topology-based, DC&mdash;DC converter includes an upper power switching N-channel device FET integrated in the same semiconductor circuit chip with the switching driver, while a lower power switching is also an N-channel FET, but is external to the driver chip. Either of the two power switching FETs may be configured to include a pilot FET cell, to facilitate current sensing for the controller.

Growing community of inventors

Cary, NC, United States of America

Greg J Miller