Cypress Semiconductor Corporation

Extreme Networks, Inc.

Parade Technologies, Ltd.

Avaya Inc.

Greg J Landry

Tao Peng

Karthik S Gopalakrishnan

Roger Lapuh

Paul Unbehagen

Zenon Kuc

John Mead

Timothy M Lacey

Massoud Badaye

Shailesh Shah

Robert M Reinschmidt

Peter Adamek

Sherif Hanna

Alan ReFalo

Jeyenth Vijayaraghavan

David Gordon Wright

Ashish Pancholy

Eric H Voelkel

Steve Kolokowsky

Rajesh Venugopal

Alan R Hawse

Embodiments generally relate to enabling configuration in networks. In one embodiment, a method includes receiving a message from an edge configuration device, wherein the message contains shortest path bridging (SPB) configuration information. The method also includes performing an intermediate system-to-intermediate system (IS-IS) configuration in response to receiving the message.

Enabling configuration in networks

Embodiments generally relate to enabling encapsulation in networks. In one embodiment, a method includes receiving a message from an edge configuration device, wherein the message contains shortest path bridging (SPB) configuration information. The method also includes performing provider backbone bridge (MAC-in-MAC) encapsulation in response to receiving the message.

Performing MAC-in-MAC encapsulation using shortest path bridging configuration information

A method for detecting force applied to a capacitive sensor array and compensating for coordinate inaccuracy due to force includes receiving a plurality of capacitance measurements from the capacitive sensor array, where the plurality of capacitance measurements includes a first capacitance measurement and a second capacitance measurement, and detecting pressure on the capacitive sensor array based on a comparison between the first capacitance measurement and the second capacitance measurement.

Flexible capacitive sensor array

A method for detecting a magnitude of force applied to a capacitive sensor array may comprise receiving a plurality of capacitance measurements affected by a contact at a touch-sensing surface, and determining a magnitude of a force applied to the touch-sensing surface at a location of the contact based on the location of the contact and a capacitance measurement of the first plurality of capacitance measurements.

Force sensing capacitive hybrid touch sensor

Embodiments generally relate to message transmission in networks. In one embodiment, a method includes enabling a user to provide shortest path bridging (SPB) configuration information. The method also includes receiving the SPB configuration information from the user. The method also includes sending the SPB configuration information to an edge server device.

Message transmission in networks

A capacitive sense array configured to improve accuracy in detecting a presence of a conductive object is described. In one embodiment the capacitive sense array includes a first set of sense elements including a plurality of sub-sections and a second set of sense elements including a plurality of sub-sections such that the plurality of sub-sections of one sense element of the first set straddle at least one of the plurality of sub-sections of at least two of the sense elements of the second set. The straddle as defined in the present invention includes shifting and interleaving sub-section of one sense element with the sub-sections of at least two sense elements adjacent to the one sense element.

Accuracy in a capacitive sense array

Embodiments described herein provide capacitive sensing devices and methods. A substrate having a plurality of pairs of conductive traces formed thereon is provided. The pairs of conductive traces include first and second conductive traces having first and second opposing ends. A capacitance variation of a plurality of the first conductive traces and a plurality of the second conductive traces is measured. The capacitance variation of at least some of the second conductive traces is measured before the capacitance variation for all of the plurality of first conductive traces is measured. A position coordinate in a two-dimensional coordinate system on the capacitive sensing device is determined based on the measuring a capacitance variation of a plurality of the first conductive traces and a plurality of the second conductive traces.

Single layer multi-touch capacitive sensor

Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

Method and circuitry to translate a differential logic signal to a CMOS logic signal

A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of cross-coupled transistors, a pair of output nodes and a first pair of load transistors. The pair of cross-coupled transistors may be coupled for receiving a pair of differential currents and for generating a pair of differential voltages, which may then be supplied to the pair of output nodes. The first pair of load transistors may have mutually-connected gate terminals, mutually-connected drain terminals, and a source terminal coupled to a different one of the output nodes. In a unique aspect of the invention, an equalization transistor may coupled between the pair of output nodes for equalizing the pair of differential voltages for a predetermined amount of time at the beginning of a sense cycle. As such, the equalization transistor may be added to prevent the current sense amplifier circuit from generating erroneous results during the predetermined time period.

Memory device, current sense amplifier, and method of operating the same

High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion

Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.

High-speed multiplexer latch

A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.

Method and an apparatus to generate static logic level output

A method and system for efficiently testing circuitry. The method and system may be applied to testing embedded memory circuit blocks within a programmable logic device (PLD). Circuitry used in the testing process can be implemented from the programmable logic resources of the PLD, or alternatively, could be provided as specialized, dedicated test mode circuitry. The PLD may contain an arbitrary number, n, of memory blocks with each block having an arbitrary number, x, of output pins. An AND-tree circuit is implemented that receives each of the n*x output pins. If any pin is low, the output of the AND-tree is low, otherwise, the output is high. The output of the AND-tree is an input/output pin of the PLD. An OR-tree circuit is implemented that receives each of the n*x output pins. If any pin is high, the output of the OR-tree is high, otherwise, the output is low. The output of the OR-tree is another input/output pin of the PLD. The OR-tree and AND-tree circuits can be used to detect any manufacturing faults within the PLD and can also be used to measure the max/min delay timing of the memory block signals. During testing, predetermined patterns of logic are loaded into the memory blocks and read back in predetermined sequences using the AND-tree and OR-tree results. Using this method and system, a tester can be used that has reduced pin count and parallel testing can be performed.

Method and system for efficiently testing circuitry

According to one embodiment, a method for programming a programmable logic device (PLD) may include reading configuration data from a memory device to program a first portion of a PLD to function as a data decompression circuit ( ). Compressed configuration data may then be read and decompressed by the first portion and used to program a second portion ( ) with a user determined function. A first portion may then be reprogrammed with a user determined function ( ).

Method and apparatus for using programmable logic device (PLD) logic for decompression of configuration data

A method of converting or translating a layout or schematic netlist to a simulation netlist, comprising the steps of identifying net-shorting elements in the layout or schematic netlist and automatically replacing at least one such net-shorting element with an RC network to generate the simulation netlist.

METHODS OF CONVERTING AND/OR TRANSLATING A LAYOUT OR CIRCUIT SCHEMATIC OR NETLIST THEREOF TO A SIMULATION SCHEMATIC OR NETLIST, AND/OR OF SIMULATING FUNCTION(S) AND/OR PERFORMANCE CHARACTERISTIC(S) OF A CIRCUIT

Growing community of inventors

Merrimack, NH, United States of America

Greg J Landry