Microchip Technology Inc.

Greg Dix

Randy L Yach

Philippe Deval

Paul Fest

Jina Shumate

Roger Melcher

Jacob Lee Williams

Harold Kline

Dan Grimm

Josh Kaufman

Francesco Mazzilli

Eric Peterson

Rajesh Nayak

A process is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) device. A TFR film is formed and annealed over an IC structure including IC elements and IC element contacts. An oxide cap is formed over the TFR film, which acts as a hardmask during a TFR etch of the TFR film to define a TFR element, which may eliminate the use of a photomask and thereby eliminate post-etch removal of photomask polymer. TFR edge spacers may be formed over lateral edges of the TFR element to insulate such TFR element edges. TFR contact openings are etched in the oxide cap over the TFR element, and a metal layer is formed over the IC structure and extending into the TFR contact openings to form metal contacts to the IC element contacts and the TFR element.

Thin film resistor (TFR) formed in an integrated circuit device using an oxide cap layer as a TFR etch hardmask

An integrated circuit device for controlling and sensing electrical current is provided. The integrated circuit device comprises a main transistor device, configured for controlling a main current, and a plurality of sensing transistor devices, configured for controlling a combined sensing current. The main transistor device and the plurality of sensing transistor devices are connected to a common gate node. The on-state resistance of the main transistor device is lower than a combined on-state resistance of the plurality of sensing transistor devices. The sensing transistor devices are distributed throughout at least a section of the integrated circuit to reduce an influence of at least one local property of the integrated circuit device on the combined sensing current.

Current sensing for integrated circuit devices

A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.

Method of forming a field-effect transistor (FET) or other semiconductor device with front-side source and drain contacts

The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

Capacitor formed on heavily doped substrate

A semiconductor power chip has a semiconductor power device formed on a semiconductor die; wherein the semiconductor power device comprises an array of conductive contact elements; a passivation layer formed over the plurality of conductive contact elements, the passivation layer comprising passivation openings over a plurality of the conductive contact elements; and an array of conductive bumps including one or more interconnection bumps, wherein each interconnection bump is formed over the passivation layer and extends into at least two of the passivation openings and into contact with at least two underlying conductive contact elements to thereby provide a conductive coupling between the at least two underlying conductive contact elements.

Bumps bonds formed as metal line interconnects in a semiconductor device

A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate.

Power field effect transistor

A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

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Tempe, AZ, United States of America

Greg Dix