Silicon Graphics, Incorporated

Atheros Communications, Inc.

Greg Chesson

Nancy Cam-Winget

Desmond W Young

Hansel A Collins

Daniel Yau

David M Parry

Jeannine Marie Smith

Paul Everhardt

Yuh-wen Lin

In-whan Choi

A method of providing a protocol for rekeying between two stations is disclosed. The method can include providing a first set of messages for computing a new key and reserving an auxiliary storage area for the new key. The first set of messages comprises an enable exchange. The method also includes providing a second set of messages to obsolete an old key and switch to the new key. The second set of messages comprises a transition exchange. In one embodiment, the protocol includes rekeying between multiple stations, and the rekey coordinator sends the first set of messages to a plurality of rekey participants. The auxiliary storage area allows multiplexing in both the enable and transition exchanges, thereby facilitating an efficient and safe rekey operation.

Rekey operation with multiplexing capability

The present invention comprises a dynamic skew compensation circuit. The present invention includes a receiver, a plurality of channel inputs built into the receiver, and a delay stack structure coupled to the plurality of channel inputs. The receiver is adapted to accept data from a parallel data transfer cable. The channel inputs couple to each of the individual communications channels which comprise the parallel data transfer cable. The delay stack structure includes a plurality of delay stacks, each coupled to a respective channel input. Each delay stack dynamically selects an additional delay amount for its respective communications channel such that each communications channel of the parallel data transfer cable is deskewed with respect to the others. In so doing, the distances across which data can be received and the speeds at which data is transferred via the parallel data transfer cable is increased.

Method and system for deskewing parallel bus channels

A data stream processing unit comprises a CPU which comprises an ALU, a shift/extract unit, timers, a scheduler, an event system, a plurality of sets of general purpose registers, a plurality of sets of special purpose registers, masquerade registers, pipeline controller, a memory controller and a pair of internal buses. The multiple sets of general and special purpose registers improves the speed of the CPU in switching between environments. The pipeline controller, the scheduler, the events system, and the masquerade registers facilitate the implementation and execution of the methods of the present invention such as efficient thread scheduling, branch delays, elimination of delay slots after stores that provide further increases in the performance and bandwidth.

Central processing unit for processing a plurality of threads using

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Palo Alto, CA, United States of America

Greg Chesson