Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Greg Alyn Unruh

Fazil Ahmad

Pin-En Su

William Huff

Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.

Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot

The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

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San Clemente, CA, United States of America

Greg Alyn Unruh