Thomson Consumer Electronics Inc.

Greg A Kranawetter

Donald Henry Willis

Timothy W Saeger

John Alan Hague

Nathaniel H Ersoz

Haoping Yu

David Lowell McNeely

Wai-Man Lam

James H Doty, Ii

A delay correction circuit includes a source of a clock signal and a source of a timing signal asynchronous with the clock signal. A timing signal detector is responsive to the clock signal and the timing signal, and is properly operative only when the timing signal is stable for a predetermined time period around the clock signal. A control circuit conditions utilization circuitry to operate after a delay time after the timing signal is detected. Adjusting circuitry conditions the control circuit to adjust the delay time if the timing signal was not stable within the predetermined time period.

Delay correction circuit

A television receiver includes an MPEG decoder for providing decoded pixel blocks. Decoded pixels are recompressed prior to storage in frame memory. In the recompression process a reference first pixel is compressed as a function of a pixel block parameter. A reconstructed reference pixel value is used in a prediction network when reconstructing remaining pixels of the pixel block prior to display. A first pixel processor accurately compresses a reference pixel which prevents the propagation of a prediction error throughout the reconstructed block.

Picture element processor for a memory management system

An M-bit digital signal, the most significant bit (MSB) thereof and an integer K are added to produce a sum which is truncated by N least significant bits to provide a symmetrically rounded bit-reduced digital output signal. The MSB may be applied in true or complemented form to the adder for selecting wide or narrow rounding modes having different numbers of output zeros disposed about a point of symmetry for a given input signal change. Advantageously, undesirable direct current (DC) shifts due to least significant bit (LSB) reduction in digital video, audio or similar applications are prevented.

Apparatus for symmetrically reducing N least significant bits of an

A digital filter (20,30) separates an M-bit (12) chrominance component (C12) from an N-bit (8) digital composite video signal (CV) supplied thereto, M (12) being greater than N (8) due to arithmetic operations (24,44,46,50) required for the separation. The separated M bit chrominance component is reduced to N-bits and subtracted from the composite video signal to provide a separated luminance component. For bit reduction, the separated chrominance component (C12) is subjected to symmetrical rounding (100A or 100B and 104) and limiting (104). Advantageously, symmetrical rounding of the chrominance component provides reduces a tendency for the luminance component to exhibit contouring when displayed.

Apparatus for separating a digital composite video signal into components

Delay matching for video data during expansion and compression

A video display control system comprises: a video display having a wide format display ratio; a letterbox detector for sampling video information in pictures represented by input video signals having a letterbox format and generating a control signal for enlarging the pictures for substantially filling the video display means with active video; and, a first control circuit for restricting operation of the letterbox detector to a vertical range of horizontal lines in each field of the video signal; and, a second control circuit for restricting operation of the letterbox detector to a horizontal range of video data in each of the horizontal lines.

Managing letterbox signals with logos and closed captions

A video display control system automatically controls a video display responsive to detection of letterbox format input video signals having varying format display ratios. A detection circuit continuously detects the first and last lines of active video in a video signal. A memory stores scan line numbers corresponding to the first and last lines of active video. The height of the picture is determined from the scan line numbers of the first and last lines of active video. The picture height is indicative of the format display ratio of the letterbox input. A comparator circuit compares the picture height to a threshold corresponding to the widest expected format display ratio of a letterbox input signal. A control circuit, for example a microprocessor, is operable in a first mode of operation for enabling the memory to continuously update the stored scan line numbers unless the picture height exceeds the threshold, and operable in a second mode of operation for enabling the memory to update the stored scan line numbers when active video is detected in a video line corresponding to a scan line number less than the stored first line or greater than the stored last line. At least one of picture size and picture cropping on the display means is controlled responsive to the picture height. A circuit for initiating the first mode of operation after the second mode of operation can operate automatically or manually.

Adaptive letterbox detector

Apparatus for measuring skew in a clock signal for processing a video signal includes a cascade connection of a plurality of analog delay elements to which the clock signal is applied. The output connections of each analog delay element is coupled to a data input terminal of a respective storage element. A signal representative of the horizontal synchronizing signal is applied to the storage elements to simultaneously latch signal into the respective storage elements, thereby capturing a representative cycle of the sampling clock signal in the storage elements. Decoding circuitry is coupled to the storage elements for detecting the relative position of the e.g., leading transition of the sampling clock pulse immediately preceding the trailing transition of the horizontal pulse A ratio is calculated indicative of the skew error, which ratio corresponds to the position of the first transition, in units of delay, divided by the duration of the sampling clock period, in units of delay. In one embodiment presented, the ratio is a measure, as a fraction of a clock period, of the time interval between a predetermined transition of the horizontal synchronizing signal and the leading transition of the first sampling clock pulse following such predetermined transition.

Apparatus for measuring skew timing errors

A video display control system, comprises a video display having a first format display ratio. A picture height circuit determines an active video picture height from an input video signal having a second format display ratio. A detector circuit identifies letterbox formats responsive to the active video picture height in the video signal and determines a format display ratio of the letterbox picture. A zoom control circuit is operable in a first mode of operation for enlarging the picture in size to fill the display substantially entirely, notwithstanding consequent cropping of the picture, and operable in a second mode of operation for enlarging the picture in size to substantially fill the display vertically, notwithstanding consequent unused portions of the display. A vertical pan control circuit automatically centers the picture in both modes of operation. The detector can identify the format display ratio of the letterbox format picture a circuit responsive to the identified format display ratio controls image aspect ratio distortion of the enlarged picture. A deflection system is controllable in vertical size by a variable vertical scan rate, in horizontal size by variable horizontal video expansion and compression, and in pan position by varying the vertical reset in phase.

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Indianapolis, IN, United States of America

Greg A Kranawetter