Micron Technology Incorporated

Mosaid Technologies Corporation

Micron Semiconductor, Inc.

Other

Round Rock Research, LLC

Greg A Blodgett

Sebastien Andre Jean

Todd A Merritt

Chang Ki Kwon

Timothy B Cowles

Donald M Morgan

Tyler J Gomm

Debra M Bell

Danilo Caraccio

Daniele Balluchi

Graziano Mirichigni

Christopher K Morzano

Dong Pan

Aaron M Schoenfeld

Brian M Shirley

Tae Hyoung Kim

Huy Thanh Vo

Yangsung Joo

Vijay Vankayala

Raghu Sreeramaneni

Stephen L Casper

Daniel R Loughmiller

Chuck Snodgrass

Tom Stamm

Apparatus and methods are disclosed, including a memory device or a memory controller configured to supply supported voltages to a host, provide temperature throttling information to the host, or provide an indication that a host attempting to read a result was not the host that caused the placement of the result in a result register. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

RPMB improvements to managed NAND

The present disclosure includes apparatuses and methods for providing energy information to memory. An embodiment includes determining, by a host, that a charge level of an energy source coupled to the host has reached or exceeded a threshold value, and transmitting, from the host to a memory device coupled to the host, signaling indicative of an energy mode for the memory device, wherein the signaling is transmitted based at least in part on determining that the charge level of the energy source has reached or exceeded the threshold.

Providing energy information to memory

Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system.

Dual mode hardware reset

Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

Replay protected memory block command queue

Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

Host accelerated operations in managed NAND devices

Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

Managed NAND performance throttling

Apparatus and methods are disclosed including a memory device or a memory controller configured to receive, from a host device over a host interface, a request for a device descriptor of a memory device, and to send to the host, over the host interface, the device descriptor, the device descriptor including voltage supply capability fields that are set to indicate supported voltages of the memory device, the supported voltages selected from a plurality of discrete voltages. The host device can utilize the supported voltages to supply an appropriate voltage to the memory device. Methods of operation are disclosed, as well as machine-readable medium, a host computing device, and other embodiments.

Managed NAND power management

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

Memory refresh methods and apparatuses

Growing community of inventors

Nampa, ID, United States of America

Greg A Blodgett