Texas Instruments Corporation

Granville E Ott

Christopher T Chang

Ron H Johns

Donald W Candy

Carlo L Herrmann

A threaded interpretive processor includes an input/output (I/O) bus (10) and an address bus (12) for carrying data thereon. An internal ROM/RAM (80) is interfaced with the I/O bus (10) and is addressable from the address bus (12). Instructions placed on the I/O bus (10) are clocked onto the address bus (12) through an instruction pointer (86) in response to a system clock (26). The data on the I/O bus (10) is also clocked to a microcode ROM (60) through an instruction register (58). The microcode ROM (60) outputs microcode instructions to control the system operation. The microcode instructions control a parameter stack (18). The parameter stack (18) consists of an eight register rotary stack (44) that has the outputs thereof simultaneously addressable by two output buses (46) and (48) and the inputs thereof addressable by an interface bus (36) and a data input bus (50). The outputs of the rotary stack (44) are input to an arithmetic logic unit (16), the output of which is input back into the rotary stack (44). Transfer gates are provided to control data flow on the output buses and input buses such that the data in the rotary stack (44) can be manipulated. Addresses of microcode instructions are sequentially placed onto the I/O bus (10) for controlling the microcode ROM (60) and the instruction pointer (86) increments this instruction address to select the next sequential instruction address. In this manner, instructions can be sequentially executed in sequential clock cycles.

Threaded interpretive data processor

A semiconductor wafer (26) may have all the integrated circuits (36) formed thereon simultaneously self-tested by the addition of a power circuit, a ground circuit and clock circuit. Lead lines are formed during metallization of the integrated circuits (36) on the wafer (26). The lead lines are interconnected to the integrated circuits (36) to form a power input, a ground input and a clock input on each integrated circuit (36). A test head (28) having a power probe (44), a ground probe (46) and clock probe (48) is attached to the power, ground and clock circuits on the semiconductor wafer (36). The integrated circuits (36) are simultaneously tested by the test head (28), and failed circuits are identified by an infrared detector (42).

Integrated circuit self-testing device and method

Disclosed is a monolithic magnetic integrated circuit. A magnetic material (22) is formed on a semiconductor substrate (10) in multiple layers to form a closed circuit. The closed circuit magnetic material (42) is formed around a deposited conductor (32) which is insulated from the magnetic circuit by silicon dioxide (34).

Method of making a monolithic integrated magnetic circuit

A method and apparatus for storing a relationship between individual elements of two or more knowledge sets includes a main computer (12) that is operable to receive a portable memory cartridge (20). The computer (12) has an input keypad (16), a storage medium (18) and a display (14). A coordinate transducer (24) is provided to input the coordinates from a test sheet (26). The test sheet (26) has a pattern of knowledge elements in a question and answer format. The relationship between the questions and answers is predetermined and is stored in the portable memory cartridge (20). The coordinate transducer (24) provides for input of the coordinates of the question and answer on the test sheet for storage in the computer. After storage, selection of the coordinates of a particular question is followed by selection of the coordinates of an answer and comparison made by the computer (12) with the stored relationship in the portable cartridge (20). A true comparison results in a correct answer and a false comparison results in an incorrect answer.

Method and apparatus for correlating test information

A complex multiplier includes a carry-sum systolic array (26) of multiplier cells for processing a multiplicand therethrough in accordance with a modified Booths algorithm. The multiplier performs two multiplications and two addition/substraction operations. A ROM (12) provides the multipliers for the operation which are input to a booth decoder (50) through a delay line (48). The delay line (48) delays pairs of bits by one bit each to synchronize with the flow of the partial products through the array (26). After one product is processed in the array (26), the sum and carry is fed back to the input through a delay (52). This delay allows for processing two products in a single operation with a subsequent operation interleaved therebetween. When one operation is complete, it is output to adders (64) and (66) to perform a complex addition and substraction with another input data vector. This addition occurs at one half the rate of the pipeline (26) due to the interleaving of the two operations.

Systolic complex multiplier

The projection display of the present invention employs a light source, a spatial light modulator such as a deformable mirror device having a plurality of individually electrically deformable mirror cells and Schlierin optics to project light from deformed mirror cells onto a viewing screen. An optical system forms light from the light source into a substantially collinear beam. A Schlierin optical device composed of alternating reflecting and transmitting portions is disposed at an angle to this beam. Light reflected or transmitted by the Schlierin optical device is focused by additional optics to a point near the deformable mirror device. Light reflected from undeformed mirror cells passes through the Schlierin optical device back to the light source. Deformed mirror cells reflect light at least in part to differing portions of the Schlierin optical device to follow a different path to a viewing screen. Control of the deformation of individual mirror cells thus enables control of illumination of corresponding spots on the viewing screen. A color picture may be formed using multiple deformable mirror devices and color filters. A three-dimensional image may be formed using multiple projection systems and a directionally reflecting screen or polarizing filters for differing deformable mirror devices with matching polarizing glasses.

Optical system for projection display using spatial light modulator

An allophone vocoder which utilizes the inherent redundancy of the spoken language together with the automatic human filtering of speech so as to obtain a speech compression and recognition system. An analog speech signal is broken up into its phoneme components and encoded for transmission. The encoded phoneme sequence has a much higher compression rate than the analog speech signal. The phonemes are then either transmitted, stored, or used to generate directly an analogous allophone sequence so as to approximate the original speech signal. Due to the inherent redundancy of the spoken language, and the filtering effect of the human ear, variations or errors in the approximations of the phonemes received from the original speech signal are inconsequential to the comprehension ability of the final allophone synthesized speech.

Allophone vocoder

The spatial light modulator drive system of the present invention permits useful light modulation, such as employed in a projection display device, with a minimum of required data input. A plurality of charge storage cells with associated charge dependent light modulator cells are disposed at the intersection of row and column conductors. The drive system alternately refreshes the data stored in a particular row and responds to external commands. The automatic refresh involves selecting a particular row via a dedicated refresh counter, reading the column data in that row, storing this data in a column latch and rewriting this data to the same row. The generation of a new display is achieved in a number of steps. A particular row is selected by externally applied data. The data type, such as number of bits and variations in shade, is also specified. The starting column for application of new display data enables this new data to be entered into the desired portion of the column latch for application to the desired light modulator cells.

Spatial light modulator drive system

A video signal generation apparatus improves the resolution of the video signal by forming additional video scan lines between the successive scan lines by combining the video attributes of adjacent scan lines. This invention is particularly applicable to video display terminals and small computing systems which employ digital memories for storing graphic characters for display via a raster scan video display device. The graphics resolution may be improved in two dimensions by combining the techniques of averaging or smoothing a graphic character generated scan line by averaging or integrating a video attribute of the scan line over a period approximating the period of a individual picture element, together with forming new scan lines by combining the video attributes of adjacent graphic character generated scan lines. In a preferred embodiment of this invention an interlace scan system is formed using graphic character generated scan lines for the first half frame and the interpolated scan lines for the second half frame.

Graphics video resolution improvement apparatus

An apparatus for encoding and decoding musical signals in digital form employs conversion to the frequency domain. Discrete Fourier transform coefficients are calculated from time domain digital data at selected frequencies which are organized in sets of octavely related frequencies. Selecting frequencies in this manner greatly reduces the data rate by eliminating coefficients for many higher frequencies without a great loss of fidelity because the provision of a predetermined number of frequencies in each octave approximates the tonal response of the human ear. A further refinement is selection of frequencies to correspond to the frequencies of musical notes where the greatest energy can be expected. The complex number discrete Fourier transform coefficients can be converted to polar form with logarithmic magnitude values resulting in a further data rate reduction because the human ear is responsive only to logarithmic amplitude and because the human ear is relatively insensitive to phase angle enabling fewer bits to be used to represent the angular part without loss of fidelity. A digital filter can be easily implemented by manipulation of the magnitude part of the discrete Fourier transform coefficients.

Frequency domain digital encoding technique for musical signals

A technique for storing and transmitting digital data in a video format includes use of chrominance and luminance portions of a video signal for transmitting data and timing information. The data is encoded according to a predetermined set of chrominance signals corresponding to a predetermined set of colors. Timing information is conveyed by a change in the luminance or brightness of the video signal. A predetermined brightness level transition determines when the chrominance signal should be decoded in order to determine which of the plurality of colors is indicated. The use of the luminance signal to transmit timing information enables the use of a decoding circuit having a relatively simple structure. In one preferred embodiment, two predetermined colors are employed to indicate either a digital one or a digital zero. It is further preferred that a frame border of a predetermined non-encoded color surround each frame of encoded color signals in order to reduce the noise sensitivity of the system during both horizontal and vertical retrace. Video signals encoded in this manner may be stored in video cassette recordings or video disk recordings or may be transmitted in the manner of ordinary television signals.

Encoding and decoding digital data in a video format

A color video signal generator includes means for selectively generating either color difference information or logic levels from the same output pins. The color video signal generator is employed in a video system which outputs either the internally generated video signal or an externally generated video signal depending on whether the color difference information or the logic levels are generated. This invention has application to video terminals and small computing systems which employ video displays to enable selective display of internally generated pictures or externally generated pictures or selective overlap of such pictures. This invention also has application to integrated circuit pin minimization by enabling an analog and a digital signal to be multiplexed on the same pin.

Video system with picture information and logic signal multiplexing

A digital computing system having an auto-incrementing memory subsystem includes one or more separate memories. Each memory in the memory subsystem has its own address counter which is automatically incremented to the next sequential address after each memory readout. In the case of plural memories, a page select enables memory readout only when a page designation portion of the address matches a unique page number associated with the memory. An automatic memory refresh is provided by a refresh address counter along with a refresh address incrementer in the case that a memory is a dynamic RAM. These features enable improved performance in the digital computing system by reducing the required CPU overhead for memory subsystem control.

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Lubbock, TX, United States of America

Granville E Ott