Adeia Semiconductor Bonding Technologies Inc.

Vertical Circuits, Inc.

Other

Grant Villavicencio

Reynaldo Co

Scott P McGrath

DeAnn Eileen Melcher

Weiping Pan

Jeffrey S Leal

Simon J S McElrea

Keith L Barrie

Wael Zohni

Suzette Keefe Pangrle

Terrence Caskey

Zongrong Liu

Scott Jay Crane

Lawrence Douglas Andrews, Jr

Yong Du

Elmer M Del Rosario

John R Bray

Roseann Alatorre

Sangil Lee

Javier A Delacruz

De Ann Eileen Melcher

Suzette K Pangrie

In a method for forming a microelectronic device, a substrate is loaded into a mold press. The substrate has a first surface and a second surface. The second surface is placed on an interior lower surface of the mold press. The substrate has a plurality of wire bond wires extending from the first surface toward an interior upper surface of the mold press. An upper surface of a mold film is indexed to the interior upper surface of the mold press. A lower surface of the mold film is punctured with tips of the plurality of wire bond wires for having the tips of the plurality of wire bond wires extending above the lower surface of the mold film into the mold film. The tips of the plurality of wire bond wires are pressed down toward the lower surface of the mold film to bend the tips over.

Pressing of wire bond wire tips to provide bent-over tips

A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.

Stiffened wires for offset BVA

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Electrical connector between die pad and z-interconnect for stacked die assemblies

According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out.

Semiconductor die array structure

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to 'bleed' laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CFplasma treatment.

Semiconductor die having fine pitch electrical interconnects

A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate.

Electrical interconnect for die stacked in zig-zag configuration

An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Wafer level surface passivation of stackable integrated circuit chips

Semiconductor die separation method

Growing community of inventors

Scotts Valley, CA, United States of America

Grant Villavicencio