Gowin Semiconductor Corporation

Grant Thomas Jennings

Jinghui Zhu

Chi Kit Cheng

Jianhua Liu

A method for providing a high-speed data communication between a host and field-programmable gate array ('FPGA') is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)

An automatic measuring system containing configurable integrated circuits is able to process information via captured images. The automatic measuring system includes a metering instrument, a camera, a recognition module, and a localization module. The metering instrument has at least one display for visually displaying a number and measures the amount of measurable substance or resources (i.e., electricity and water) consumed. The camera captures an image of the number representing at least a portion the amount of measurable substance. The recognition module is operable to generate a value in response to the image and the coordinates wherein the coordinates are used to decode the image via restoring captured image to the original readout counter value. The localization module is removably or remotely coupled to the camera and operable to generate the coordinates in accordance with the image captured by the camera.

Method and system for automatic detection and recognition of a digital image

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Method and apparatus for providing multiple power domains in a programmable semiconductor device

A system containing a host and a device having a field-programmable gate array ('FPGA') is disclosed. The system includes a set of configurable logic blocks (“LBs”), a bus, and a Universal Serial Bus (“USB”) interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.

Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA)

An interface bridging device ('IBD') capable of facilitating data conversion between data streams of D physical layer (“D-PHY”) and data streams of C physical layer (“C-PHY”) is disclosed. IBD includes a first integrated circuit (“IC”) component, a bridge component, and a second IC component. The first IC component is able to process digital information and is configured to generate a first data stream formatted in D-PHY data stream. The bridge component receives the first data via a D-PHY bus and subsequently converts the first data stream to a second data stream formatted in a C-PHY data stream. The second IC component is configured to obtain the second data stream via a C-PHY bus.

Method and apparatus for providing a bridging device for interfacing between D-PHY and C-PHY

A method and/or process of interface bridging device for providing a C physical layer ('C-PHY') input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.

Method and apparatus for providing C-PHY interface via FPGA IO interface

An integrated circuit ('IC') module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

Method and apparatus for providing field-programmable gate array (FPGA) integrated circuit (IC) package

A system containing a host and a device having a field-programmable gate array ('FPGA') is disclosed. The system includes a set of configurable logic blocks ('LBs'), a bus, and a Universal Serial Bus ('USB') interface. The configurable LBs, in one aspect, are able to be selectively programmed to perform one or more logic functions. The bus contains a P-channel and an N-channel operable to transmit signals in accordance with a high-speed USB protocol. The USB interface is configured to include a first differential comparator operable to identify a logic zero state at the P-channel and a second differential comparator operable to identify a logic zero state at the N-channel.

Method and apparatus for providing multiple power domains to a programmable semiconductor device

A system architecture based on SoC FPGA for edge artificial intelligence computing includes an MCU subsystem and an FPGA subsystem. The FPGA subsystem includes: an accelerator for accelerating artificial intelligence algorithm; and a shared memory used as an interface between the accelerator and the MCU subsystem. The shared memory is configured to upload the data to be calculated and to retrieve the operation result; the accelerator is configured to read the data from the shared memory independently and to write back the operation result. The system architecture has the advantages of small hardware area, low power consumption, high computing performance and easy use, and the design process is simple and flexible.

System architecture based on SoC FPGA for edge artificial intelligence computing

Method and apparatus for providing multiple power domains a programmable semiconductor device

A method for providing a high-speed data communication between a host and field-programmable gate array ('FPGA') is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus ('USB') protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (&#x201c;LBs&#x201d;) in FPGA.

Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)

Growing community of inventors

Austin, TX, United States of America

Grant Thomas Jennings