Intel Corporation

Grant E Haab

Sanjiv M Shah

Paul M Petersen

Hong Wang

Milind Baburao Girkar

John Thomas Shen

Perry H Wang

Xinmin Tian

Daniel M Lavery

Gerolf F Hoflehner

David K Poulsen

Shih-wei Liao

Dongkeun Kim

Hideki Saito

The present disclosure relates to acquiring and releasing a shared resource via a lock semaphore and, more particularly, to acquiring and releasing a shared resource via a lock semaphore utilizing a state machine.

Low-contention lock

Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Methods and apparatus for reducing memory latency in a software application

A method and apparatus for a atomic operation is described. A method comprises receiving a first program unit in a parallel computing environment, the first program unit including a memory update operation to be performed atomically, the memory update operation having an operand, the operand being of a data-type and of a data size, and translating the first program unit into a second program unit, the second program unit to associate the memory update operation with a set of one or more low-level instructions upon determining that the data size of the operand is supported by the set of low-level instructions, the set of low-level instructions to ensure atomicity of the memory update operation.

Method and apparatus for an atomic operation in a parallel computing environment

Growing community of inventors

Mahomet, IL, United States of America

Grant E Haab