Zilog, Inc.

Grant B Richards

Gyle Dee Yearsley

Stephen H Chan

Boubekeur Benhamida

Jim Nobugaki

Delnis L Miranda

A dual latch character pacing circuit on a semiconductor chip controls data transfer between a pair of microprocessor which have significantly different data transfer rates. A first and second latch are connected in a parallel data path between the two microprocessor. The timing circuit includes a flip-flop which clocks the data between the latches. A one-shot timer is re-started on each transfer of data thereby insuring that the rate of transfer is substantially constant over a character period.

Dual latch data transfer pacing logic using a timer to maintain a data

Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.

Delayed FIFO status for serial shift emulation

A mask value generator is used to produce a mask value for deencrypting encrypted instructions from a memory. This encryption mask generator can produce a encryption mask value from a seed value and a program counter value. The seed value can stored in a memory outside the core microprocessor. The encryption mask value can be used to deencrypt instructions in an 'exclusive or' logic section.

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Meridian, ID, United States of America

Grant B Richards