Lsi Corporation

Lsi Logic Corporation

Other

Grant A Lindberg

Gregor J Martin

Ying Chun He

David Asson

Jonathan W Byrn

Stefan Graef

Arun K Gunda

Kaushik De

Mina Yoo

Sharad Prasad

A hook is attached to a carabineer via a mechanism which allows the hook to be deployed to function as a hook or stowed in a compact configuration. The combined carabineer-hook can be used to clip together more than one item or the hook can be deployed, the carabineer portion can be clipped to one item, the hook can be engaged with a surface, and the item can then be hung off of the hook. In addition, the hook can be deployed to hold one or more items while the carabineer is used to clip to another item (such as a ring, cable, rope, rail, etc.).

Multi-function hook and carabineer

A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.

I/O planning with lock and insertion features

A method for defining valid placement of intellectual property (IP) blocks within a platform application specific integrated circuit comprising the steps of (A) extracting IP recorded information for an intellectual property (IP) block to be placed on a platform application specific integrated circuit, (B) extracting device data for the platform application specific integrated circuit and (C) determining one or more valid placement locations for the intellectual property (IP) block based upon the IP recorded information and the device data.

IP placement validation

A method for estimating resources during design planning is generally provided. A first step generally involves receiving design information for an integrated circuit design. A first portion of the integrated circuit design is generally complete, while a second portion of the integrated circuit design is generally incomplete. A second step generally involves receiving user input of estimated design information for the second portion of the integrated circuit design. A third step generally involves automatically generating one or more representative blocks representing the second portion of the integrated circuit design based on the user input. The one or more representative blocks may be generated having substantially equivalent size and characteristics to one or more actual blocks developed for the second portion of the integrated circuit design.

Resource estimation for design planning

A design tool for generating design views of a semiconductor chip is presented. The design tool includes an input module, a generation module, a first synthesis module, a user interface module and an extraction module. The input module may be configured to receive input including physical and logical resources and a custom chip specification. The generation module may be configured to generate Register Transfer Level (RTL) views for the semiconductor chip. The first synthesis module may be configured to perform logic synthesis using the RTL views. The user interface module may be configured to query a user whether re-usable intellectual property (IP) is to be generated. The extraction module may be configured to extract and package design information for the re-usable IP in response to a request from the user.

Enabling efficient design reuse in platform ASICs

A method and tool that capture, create, and integrate a clock specification to achieve a correct-by-construction design flow of a semiconductor product from a partially manufactured semiconductor platform. The clocking elements of the design flow are combined and displayed in a plurality of context-driven views. Within each view, details of the clock specification are presented in the context of the information. A user may zoom in/out through the plurality of views of the design flow for more or less detailed information. Each view can combine the logical, structural, architectural, cost, timing, and other features of the clock in a particular context. A user can zoom in to select and manipulate circuit elements. The user can then zoom out and the present invention determines how changes affect other clocks in the same or other modules and/or the same clock in other modules.

Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit

A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.

Floorplan visualization method using gate count and gate density estimations

Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.

Delay/load estimation for use in integrated circuit design

A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).

Growing community of inventors

Santa Clara, CA, United States of America

Grant A Lindberg