Intersil Corporation

Other

Micrel, Incorporated

Microunity Systems Engineering, Inc.

Graham Y Mostyn

Mohammad Yunus

Alan G Corry

Wan-Thai Hsu

John Ryan Clark

Andrew Robert Brown

Jean-Yves Michel

William Cochrane Ingle

Jerald R Bernacchi

A method of configuring a device comprising a MEMS resonator includes initiating operation of the device, estimating a first parameter of the MEMS resonator based on the initiated operation, the first parameter not varying with the bias voltage, monitoring the operation of the device at a plurality of levels of the bias voltage, calculating a second parameter of the MEMS resonator based on the monitored operation, the second parameter varying with the bias voltage, determining an operational level of the bias voltage based on the estimated first parameter and the calculated second parameter, and configuring the device in accordance with the determined operational level of the bias voltage.

Bias voltage tuning of MEMS resonator operation point

The present invention encompasses techniques for reducing digital noise in integrated circuits and circuit assemblies, particularly dense mixed-signal integrated circuits, based upon shaping the noise from the digital circuit and concentrating it in a single, or a small number, of parts of the frequency spectrum. Generally, the presence of noise in the analog circuit is less important at certain frequencies, and therefore the spectral peak or peaks from the digital circuit can be carefully placed to result in little or no interference. As an example, a radio receiver might be designed such that the peaks of the digital noise lie between received channels, outside the band edges of each.

Noise reduction in integrated circuits and circuit assemblies

A circuit and method for avoiding latch up in an integrated circuit in which the base-emitter junction of a parasitic bipolar transistor forming part of a parasitic SCR structure is monitored. If the forward bias of the monitored base-emitter junction approaches a predetermined value, the operation of the circuit is altered to prevent activation of the SCR.

Structure and method for preventing latch-up in integrated circuits

The duration of time during which an AC power voltage sinusoidal waveform remains between negative voltage threshold -V1 volts, nominally 5% of negative peak voltage -V2 volts, and positive voltage threshold +V1 volts, nominally 5% of peak positive voltage +V2 volts, is detected. By the change in voltage with time exhibited by a sinusoidal waveform in the region of zero voltage crossing, the expected time duration between voltage thresholds in approximately 5% of one-half period of such sinusoidal waveform. If the actual time between voltage thresholds exceeds (nominally) twice this value, or 10% of one-half period, then a power black-out condition is sensed, and a power fault signal is produced.

Alternating current power loss detector

Disclosed is an improved efficiency switching voltage converter system wherein the semiconductor switching device employed therein is provided with increased gate drive by selectively applying the most effective driving voltage available in the system.

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Saratoga, CA, United States of America

Graham Y Mostyn