Canon Kabushiki Kaisha

Canon Information Systems Research Australia Pty. Ltd.

Graham Stoney

Timothy Merrick Long

Christopher Amies

A printing system is disclosed, the system including a receiving hardware interface () for coupling page description data to an interpreter () said interpreter interpreting the page description data to thereby output a display list to a renderer software interface () which processes the display list to thereby output a processed display list, and rendering hardware () for processing the processed display list to thereby output raw pixel data, wherein the receiving hardware interface (), the interpreter (), the rendering software interface (), and the rendering hardware () are arranged to operate in a pipelined manner, being thereby capable of concurrently processing job data from at least one page of the print job.

Highly pipelined printing system architecture

A method of dynamically allocating blocks of memory in a computer system ( ) is disclosed. The method includes the following steps. Firstly, generating a first memory allocation list in which free memory blocks (S) are recorded on the basis of size. Secondly, generating a second memory allocation list in which free memory blocks (S) are recorded on the basis of memory block address (b). When a memory block (S) is requested by the computer system, searching the first list to determine a suitably sized memory block, allocating the requested memory block from the suitably sized memory block in response to the request, and updating the first and second lists to take the allocation into account. When a memory block (S) is freed by the computer system ( ) it is determined whether a free memory block exists adjacent the freed memory block by searching the second list. In the event that one or more free memory blocks exist adjacent the freed memory block, the freed memory block and free memory blocks are merged together to form a unitary free memory block. Finally, the first and second lists are updated to take the freed memory block and any free memory block merges therewith into account.

Efficient memory allocator utilizing a dual free-list structure

The present invention discloses a method of controlling the interaction of a host CPU (,) and at least one co-processor (,) in a computer system (,) to permit substantially simultaneous decoupled execution of CPU instructions and co-processor instructions. The co-processor instructions to be executed, and those which have been executed are allocated to respective queues (,). From time to time the latter queue (,) is cleaned up under control of the CPU (,) to release memory resources previously allocated to the co-processor by the CPU. This dynamic memory management arrangement preferably includes an instruction generator (,), a memory manager (,) and a queue manager (,).

Coprocessor interface having pending instructions queue and clean-up queue and dynamically allocating memory

A method of updating, directing or moving page table entry values in a virtual memory management system. The method operates without requiring suspension of a search process looking for a predetermined page table entry value of a page table. In a first step, the method determines whether the current page table value is the predetermined page table entry value or whether the search process looking for a page table entry value is in progress. Then, the current page table entry value is deleted or moved in the event that the current page table entry value is not the predetermined page table entry value or in the event that the search process is not in progress. Next, the method waits until the search process has completed looking for the predetermined page table entry value or for a predetermined period of time before deleting or moving the current page table entry value, in the event that the current page table entry value is the predetermined page table entry value or in the event that the search process looking for a page table entry value is in progress.

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Carlingford, Australia

Graham Stoney