Texas Instruments Corporation

Graham S Tubbs

James E Ponder

Perry Wyan Lou

David J McElroy

George L Brantingham

Martin D Daniels

Joe F Sexton

Luat Q Pham

Jeffrey R Teza

Daniel L Essig

Lawrence J Housey, Jr

Stephen A Farnow

Charles J Southard

Ronald Walther

Robert Schaaf

A multi-level logic circuit includes a first plurality of logic circuits that are connected in a cascade arrangement. A second plurality of dummy logic circuits also connected in casacade arrangement are used to generate logic pulses for evaluating the first plurality of logic circuits. A clock source provides a precharged signal to the first plurality of logic circuits and the second plurality of dummy logic circuits and an evaluation circuit is used to combine the clock signal with an output signal from the dummy logic signal to obtain an evaluation signal for evaluating the logic states of the first plurality of logic circuits.

Dummy load controlled multilevel logic single clock logic circuit

A logic circuit that has a plurality of stages that are driven by a clock source that provides at least 2 clock signals and includes at least a single latch stage located between two of the plurality of stages is configured with field effect transistor technology. The latch stage includes an isolation means for isolating the preceding circuit of the plurality of stages from flow-through of the clocks and signals that are connected to the latch stage, and a latch circuit for storing the data that is applied to the latch stage between clock pulses. A plurality of latch stages can easily be configured as a shift register latch.

Level sensitive latch stage

A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm for implementing the digital multiplication of two numbers and includes a Booth recoder for recoding the multiplier into a selected number, n, of Booth operation sets where n is a positive integer that equals one-half the number of bits in the multiplier. Each operation set is applied to a second plurality of n partial products selectors which are connected in cascade arrangement according to multiplicand sets and wherein each partial product selector multiplicand set implements one of the recoded Booth operation sets. The outputs of the partial product selectors are summed by a summation means and a domino circuit means provides an evaluation pulse for each member of the partial product selector at the completion of the Booth operation set that is connected to the partial product selector.

Digital multiplication circuit for use in a microprocessor

A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.

Data processing system integrated circuit having modular memory add-on

An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

CMOS Integrated circuit device

A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal and external RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. In yet another embodiment, the clocked CMOS logic of the system is forced to a designer predefined output logic level in the inactive power down mode. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved. Power consumption less than conventional CMOS is obtainable.

Turn-off-processor between keystrokes

An MOS read only memory or ROM of small cell size is formed by a process compatible with standard N-channel silicon gate ROM manufacturing methods. In an array of rows and columns of the cells, the row address lines and gates are polysilicon, and column lines forming output and ground are defined by elongated N+ regions which are partly diffused and partly implanted since the column lines cross beneath the polysilicon row address strips. Each potential MOS transistor in the array is programmed to be a logic '1' or a '0' by the presence or absence of moat beneath the gate of a cell.

N-Channel silicon gate virtual ground ROM

An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. The source and drain regions, N+ or P+, are defined prior to the polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Method of making CMOS device allowing three-level interconnects

Method of making CMOS integrated circuit device

An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Three level interconnect process for manufacture of integrated circuit

An MOS memory cell of the pseudo static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series transistors connecting storage nodes to a supply voltage. The storage nodes are connected to complimentary data lines by a pair of coupling transistors controlled by a word address. The series transistors are turned on in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. The series transistors are not used for read or write operations.

Pseudo-static semiconductor memory cell

An electronic digital processor fabricated on a single MOS/LSI semiconductor chip includes an arithmetic unit operating on digits one at a time, with a carry output and a carry input. Commands for operating the processor are produced by decoding instruction words one at a time from a large instruction memory. A special status circuit is responsive to commands from instruction words to operate in several conditional modes. A carry input to the arithmetic unit is generated in response to whether carries were generated in either the current or previous digits being processed. Another status circuit provides the input for a conditional branch or call depending on whether a carry or compare logic signal is applied to the status circuit.

Digital processor system with conditional carry and status function in

A digital processor which may be used in a calculator is provided by an MOS/LSI semiconductive chip which contains a bit-parallel arithmetic unit for operating on data stored in a random access memory. Selector units determine which of several sources produce the inputs to the arithmetic unit. The random access memory has X and Y, or page and word addressing. Part of the random access memory provides direct access for readout. Numerical data at the Y address in the direct access memory is always available at the selector units for input to the arithmetic unit, at the same time that data at the same Y address but another X address is read out to be also an input to the arithmetic unit. The direct access part of the memory is addressed for write in by the same addressing means as the remainder of the memory. This arrangement reduces the number of machine cycles needed for arithmetic operations, and so provides faster calculations.

Digital processor system with direct access memory

An electronic calculator with a power supply ON-OFF arrangement actuated by momentary-closure push-button switches which are part of the keyboard. A bistable latch circuit on the calculator chip is continuously powered by the battery, and is caused to flip to an ON condition by actuating an ON key, and this turns on an oscillator, the output of which is pumped up to a level above the battery, and the high level voltage is used to drive a large, low-resistance transistor. This transistor is in series with the voltage supply line going to all of the other electronic circuitry on the chip. The oscillator and pump circuit assure that the drop across the transistor is negligible.

Switching control circuits for electronic calculator with push-button

A digital processor which may be used in a calculator or the like is provided by an MOS/LSI semiconductor chip which contains a ROM or read-only-memory for storing instructions, a bit-parallel arithmetic unit for operating on data stored in a random access memory and control circuitry for defining the operation of the system. The control circuitry includes a programmable logic array for decoding instruction words. Space on the chip is saved by a time-shared decoder which forms part of the programmable logic array and also decodes addresses for the ROM.

Growing community of inventors

Houston, TX, United States of America

Graham S Tubbs