Micron Technology Incorporated

Intel Corporation

National Semiconductor Corporation

Graham Richard Wolstenholme

Fernando N Gonzalez

Raymond A Turi

Trung Tri Doan

Tyler A Lowrey

Chang Wan Ha

Deepak Thimmegowda

Paolo Tessariol

Kelly T Hurley

Guy T Blalock

Aaron S Yip

Charles L Ingalls

Chun Chen

Kirk D Prall

Albert M Bergemont

Paul J Rudeck

Russell C Zahorik

Robert C Carr

Mark Alan Helm

Michael A Smith

Sukesh Sandhu

Xianfeng Zhou

Tomoharu Tanaka

Akira Goda

Steven T Harshfield

Etan Shacham

Donwon Park

Alan R Reinberg

George Matamis

Lifang Xu

Philip J Ireland

Jian Li

Nancy M Lomeli

Zengtao T Liu

Gregg Rettschlag

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Devices including stair step structures, and related memory devices and electronic systems

Methods of forming memory devices including stair step structures

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Devices including stair step structures, and related apparatuses and memory devices

Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

Microelectronic devices with symmetrically distributed staircase stadiums and related systems and methods

Memory devices including stair step or tiered structures and related methods

Memory devices and related methods

Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to different memory blocks (e.g., multiple memory blocks per string). For example, a first set of memory cells of a string may be included in a first memory block, and a second set of memory cells of the string may be included in a second memory block. The memory device may include separator wordlines disposed between wordlines associated with the first memory block and wordlines associated with the second memory block. The separator wordlines may receive different bias voltages during various operations of the memory device. Additionally, a wordline biasing scheme may be selected to program the first memory block based on whether the second memory block is programmed. Other embodiments may be described and/or claimed.

Multiple blocks per string in 3D NAND memory

Methods of forming conductive structures including stair step or tiered structures having conductive portions

Stair step formation using at least two masks

Conductive structures, systems and devices including conductive structures and related methods

Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.

Pillar arrangement in NAND memory

Growing community of inventors

Boise, ID, United States of America

Graham Richard Wolstenholme