International Business Machines Corporation

Motorola Corporation

Graham R Murphy

David P Burgess

Milton M Hood, Jr

Marvin A Denman

Seungyoon P Song

Betty Y Kikuta

Mark A Kearney

Lavanya Kling

The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.

Data processor with an execution unit for performing load instructions

A store queue for use in a data processor (10) with a memory storage system has a first-in-first-out ('FIFO') queue (48) and control circuitry (52). The control circuitry maintains three pointers which index the entries in the FIFO queue: a dispatch pointer (D), a completion pointer (C), and an oldest miss pointer (OM). The control circuitry stores each stole instruction in the entry designated by the dispatch pointer and then increments the dispatch pointer. The control circuitry increments the completion pointer when the data processor indicates that the previously designated store instruction is the oldest instruction in the data processor: when the instruction is 'completed.' The control circuitry increments the oldest miss pointer after it presents the previously designated store instruction to the memory system.

Data processor with unified store queue permitting hit under miss memory

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Austin, TX, United States of America

Graham R Murphy