Csr Technology Inc.

Zoran Corporation

Graham R Leach

Rolf Sundblad

Gordon A Wilson

A PLL circuit () for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump () is arranged to generate an output signal based on the up and down signals and a loop filter () is arranged to generate a frequency-control signal based on the output signal of the charge pump (). Furthermore, a VCO () is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO () is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz. A programmable first frequency divider () is arranged to generate the pixel-clock signal by frequency division of the oscillating signal, and a programmable second frequency divider () is arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.

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Swindon, United Kingdom

Graham R Leach