Texas Instruments Corporation

Graham M Barr

Richard D Simpson

Erick D Oakland

A floating point normalization circuit and method decodes the exponent generating a coded multibit output corresponding to the maximum decrease in the exponent within the minimum expressible exponent. This coded multibit output is bit-wise ORed with the mantissa. A left most one circuit detects the bit position of the most significant bit of the logical OR output having a '1'. The mantissa and exponent are them normalized according to this number. The mantissa is left shifted an amount equal to this detected bit position of a most significant bit having a '1'. The exponent is decremented an amount equal to this detected bit position of a most significant bit having a '1'. The exponent decoder generates said coded multibit output in the form of a mantissa equal to the minimum mantissa that can be normalized for the input exponent part of the floating point number. This minimum mantissa is equal to 2.sup.(M+N), where M is the minimum expressible exponent and N is the exponent. In the preferred embodiment, the exponent decoder includes a two to four line decoder for each pair of bits of the exponent part of the floating point number, and an AND gate connected to selected outputs of said two to four line decoders for each bit of said mantissa.

Growing community of inventors

Raunds, United Kingdom

Graham M Barr