Xilinx, Inc.

Graham Johnston

David I Lawrie

Robert Edwin Payne

Approaches are disclosed for encoding N symbols of a sequence in parallel using an R parity symbol encoding algorithm. A first symbol matrix is added to a first parity matrix over a finite field to produce a first intermediate matrix. The first intermediate matrix is multiplied by at least a first coefficient matrix and a second coefficient matrix over the finite field to produce a second intermediate matrix. A second symbol matrix is multiplied by at least the second coefficient matrix to produce a third intermediate matrix. The second and third intermediate matrices are added to produce a revised parity matrix.

Circuit for forward error correction encoding of data blocks

In one embodiment, an encoder circuit is provided. The encoder includes an input circuit having a plurality of finite field subtraction circuits, each configured to receive a respective one of the sequence of symbols and subtract the symbol from a respective symbol of an intermediate polynomial to produce a respective feedback symbol. For each coefficient of a code generation polynomial, a first circuit is configured to multiply each feedback symbol by a respective constant corresponding to the coefficient to produce a first set of intermediate results. Each first set of intermediate results is summed to produce a second intermediate result. A buffer circuit of the encoder is configured and arranged to store the second intermediate results produced by the first circuit as the intermediate polynomial.

In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to one or more of the decoder stages and is configured to generate, for each of one or more of the plurality of decoder stages, a respective compressed error mask from the error mask produced by the decoder stage. A buffer circuit is coupled to the compression circuit and is configured to buffer the compressed error masks. A decompression circuit is coupled to the buffer circuit and is configured to decompress each of the compressed error masks. A combination circuit is coupled to the decompression circuit and is configured to combine the decompressed error masks into a single error mask.

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Edinburgh, United Kingdom

Graham Johnston