Pulsic Limited

Graham Balsdon

Mark Waller

Jeremy Birch

Tim Parker

Mark Williams

Fumiaki Sato

Fumiako Sato

Robert Eisenstadt

Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Filling vacant areas of an integrated circuit design

Filing vacant areas of an integrated circuit design

A technique generates small scale clock trees using a spine-based architecture (using spine routing) while also using clustered placement. Techniques are used to control clock sink cluster contents in order to minimize clock skew, minimize clock buffer count, and minimize use of routing resources. This approach also provides the user with ample structure and control to customize small efficient clock trees, and can also reduce clock power consumption.

Clock tree generation and routing

A technique will automatically route interconnect of an integrated circuit and adjust spacing between tracks or interconnect in order to improve performance or reduce electromigration effects. By increasing spacing between certain tracks or moving tracks, performance can improve because a track will be more noise immunity from nearby tracks on the same layer or on different layers. The automatic router will adjust spacing between tracks depending on one or more factors. These factors may include current associated with a track, width of a track, capacitance, inductance, and electromigration. In a specific implementation, the technique uses a shape-based approach where a grid is not used. The technique may further vary the width of the tracks.

Automatically routing nets with variable spacing

A system of automatically routing interconnect of a integrated circuit design while taking into consideration the parasitic issues of the wiring as it is created. The system will be able to select an appropriate wiring pattern so that signals meet their performance requirements.

Automatically routing nets according to parasitic constraint rules

A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.

Automation using spine routing

A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density and a frequency of each net, the technique will determine the current requirements for each net. In an implementation, the technique forms a Steiner tree for a net, and routs using the Steiner tree. The technique widens nets having greater current requirements; adjacent wiring may be pushed aside to create sufficient space for wider nets.

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Glos, United Kingdom

Graham Balsdon