Meridian Semiconductor, Inc.

United Microelectronics Corp.

Ampere Computing LLC

Graham B Whitted, Iii

Hsiao-Shih Chang

James A Kane

Kha Hong Nguyen

Phil Mitchell

Sean Philip Mirkes

Brian Thomas Chase

Hsiao Shih Chang

Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.

Distributing a global counter value in a multi-socket system-on-chip complex

A floating-point processor and method detect a sticky bit during a floating point operation. The floating-point processor includes a sticky bit predictor circuit, a bit scanner, an exponent arithmetic circuit, and a mantissa arithmetic logic circuit. Input and output circuitry allow the floating-point processor to communicate with another processor. The bit scanner generates sticky significance values corresponding to the operands. When adding two operands, the sticky bit predictor circuit compares the sticky significance value of the smaller operand with an alignment value in order determine whether to set the sticky bit.

Sticky bit detector for a floating-point processor

An instruction combination unit for a microprocessor compares multiple fetched instructions to determine whether they can be combined for simultaneous execution. The instruction combination unit compares destination registers of preceding instructions against source registers of subsequent instructions. If a subsequent instruction is to operate on a result of a preceding instruction before the result of the preceding instruction is available to the subsequent instruction, a data access conflict arises. The instructions are compared, and combined, if possible. Otherwise, execution of the subsequent instruction is stalled until the result from the preceding instruction is available to the subsequent instruction.

Method and apparatus for simultaneously executing instructions in a

A protection mechanism for a microprocessor has multiple privilege levels for tasks running on the microprocessor. A memory control unit for the microprocessor includes segment registers that identify segments of memory assigned to various tasks. When a segment register is loaded with the address of a new segment for a task, the protection mechanism within the memory control unit compares the privilege level of the task requesting the segment with the privilege level of the requested memory segment and determines whether the requested memory segment can be assigned to the requesting task. The relationship between the privilege levels is programmable to provide flexibility in generating privilege faults.

Method and apparatus for detecting memory segment violations in a

A segment limit check circuit performs limit checks on fetch addresses generated by a CPU. The circuit and method for performing the fetch limit check are simplified over the prior art by effectively moving the fetch limit check to linear address space. For a microprocessor that uses physical addresses of 32-bits and performs fetches as 16-byte aligned accesses, the circuit of the present invention generates a 33-bit linear address and a 33-bit upper limit value. A comparator compares the upper 29 bits of the linear address with the upper 29-bits of the upper limit value. If a match occurs, the circuit decodes the 4 low-order bits of the upper limit value to determine which of the 16 instruction bytes (if any) fall outside the segment limit.

Circuit and method for detecting segment limit errors for code fetches

A microprocessor circuit monitors addresses generated by the microprocessor to check for various address-exception conditions. Fetch-exception status bits are generated for each instruction byte to indicate whether an address-exception was detected for each respective byte address. Once fetches are performed, the fetch-exception status bits are fed to an instruction buffer with the corresponding instruction bytes, where they are maintained until execution. Decode logic of an instruction control unit analyzes the fetch-exception status bits upon execution, and generates exceptions before the corresponding exception-causing instructions are executed. Address-exceptions occurring as the result of operand accesses are handled immediately. The operand access causing the exception is aborted, and the decode of the following instruction is modified to generate a micro-interrupt. A micro-interrupt routine determines the cause of the interrupt, and generates the appropriate exception. For breakpoint exceptions on operand accesses, the micro-interrupt routine re-executes the breakpoint-causing instruction to completion before generating the appropriate exception.

Exception handling circuit and method

An access control unit for a microprocessor receives fetch requests and operand access requests from a CPU of the microprocessor, and issues the requests to a bus/cache unit in a manner which reduces interference between fetch requests and operand access requests. Fetch addresses for fetch requests that cannot be immediately performed by the bus/cache unit are placed in a fetch address queue, allowing such fetch requests to be postponed. Operand access requests received by the access control unit are performed prior to postponed fetch requests. Thus, the execution unit of the CPU can continue to execute instructions which require operand accesses without waiting for pending fetch requests to be performed. Fetch requests that have been postponed by the access control unit are attempted on every clock cycle for which no operand access request is pending.

Circuit and method for reducing delays associated with contention

A circuit and method suspend the operation of a CPU of a microprocessor while a memory control unit (MCU) of the microprocessor performs certain operations for the CPU. The circuit is used to generate two internal clock signals from an external clock signal generated off-chip. The first internal clock signal is used to control the MCU and runs continuously. The second internal clock signal is used to control the CPU. During MCU operations requiring wait states, a stall circuit stalls the second internal clock to suspend the operation of the CPU and to thereby prevent CPU register values from changing. The circuit and method eliminate the need for certain data circulation logic within the CPU.

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Irvine, CA, United States of America

Graham B Whitted, Iii