USA as Represented by Secretary of the Navy

Graham A Garcia

Ronald Eugene Reedy

Stephen Douglas Russell

George P Imthurn

Randy L Shimabukuro

Paul R De La Houssaye

Howard W Walker

Isaac Lagnado

Andrew Thomas Barfknecht

Michael J Burns

Stanley R Clayton

Mark L Burgener

Steven J Cowen

David W Brock

Shannon D Kasa

Larry D Flesner

Patrick A Shoemaker

Michael R Brininstool

Narayan R Joshi

Michael E Stewart

A high gain phototransistor uses lateral and vertical transistor structures and a triple base. The base regions of two vertical structures are in the bulk of a semiconductor substrate while the base of a single lateral structure is adjacent a light receiving phototransistor surface. Minority carrier generation extends from the base region of the lateral transistor to the base regions of the vertical transistors and is present in the vertical regions within a diffusion length of the optically generated carriers of the lateral base. The bases of all three transistor structures are electrically connected. The collector electrodes of one of the vertical structures and the lateral structure are electrically connected, while the emitter electrodes of the other of the vertical structures and the lateral structures are electrically connected. Finally, the remaining vertical collector and emitter electrodes are electrically connected via a buried layer adjacent the phototransistor wafer substrate.

Triple base bipolar phototransistor

The invention is designed to employ one or a multitude of sensors designed to allow operational monitoring of any of a variety of electromagnetic radiating tubes. Monitoring is conducted to detect a degradation in performance which can be used as a factor in deciding whether tube replacement is justified. Contrary to some past approaches that focused on averaged tube outputs, the invention is designed to examine individual tube pulses.

Method and apparatus for discerning degradation of electromagnetic radiating tubes

A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Method for making a monolithic integrated high-T.sub.c

A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Monolithic integrated high-T.sub.c superconductor-semiconductor structure

A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions. A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Semiconductor-on-insulator device interconnects

A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer and another layer of silicon dioxide on a layer of high minority carrier lifetime silicon of a bulk silicon device wafer. The silicon dioxide layers are placed in contact and annealed to form a bonded structure having an annealed layer of silicon dioxide. The layer of bulk silicon is then thinned. The thinned layer of bulk silicon and the annealed silicon dioxide layer are patterned by photolithography to form mesas of high minority carrier lifetime silicon and to expose regions of low minority carrier lifetime silicon on the bonded structure.

Low and high minority carrier lifetime layers in a single semiconductor

Method for forming low and high minority carrier lifetime layers in a

The present invention provides a method for fabricating a silicon-on-insulator voltage multiplier. The method comprises the steps of: forming a first silicon layer having a first concentration of a first dopant with a first polarity on a silicon wafer having a second concentration of a second dopant with a second polarity opposite the first polarity to create a diode junction; forming a second silicon layer on the first silicon layer, the second silicon layer having a third concentration of a third dopant having the first polarity, where the third concentration is greater than the first concentration of the first dopant; forming a silicon dioxide layer on the second silicon layer by thermal oxidation; bonding an insulating substrate to the silicon dioxide layer to create a bonded wafer, where the insulating substrate is selected from the group consisting of quartz, glass, sapphire, and silicon dioxide on silicon; thinning the silicon wafer to form a thinned silicon layer; etching the bonded wafer to form a plurality of separate diodes having sloped sidewalls and to expose selected regions of the insulating substrate; forming an insulating silicon layer on the selected regions of the insulating substrate and on the separate diodes; exposing selected regions of the thinned silicon layer and regions of the second silicon layer of each of the diodes; and forming metal interconnects between the exposed selected regions of the thinned silicon layer of one of the diodes with the silicon layer of another of the diodes.

Method for fabricating a silicon-on-insulator voltage multiplier

An integrated circuit memory element is capable of storing analog information. The memory value can be increased and decreased incrementally with no knowledge of the current state and may be stored for a long period of time. Analog memory information is stored as an electrical charge on a floating gate structure and modification of this information is accomplished by the use of hot-carrier injection to transport electrons off of as well as onto the floating gate (to erase as well as to program electrically). Charge is written onto and off of the gate by injection capacitors in deep depletion and is accomplished by having the floating gate contiguous with a piece of crystalline p-type silicon, in which a deep-depletion region may be formed so that hot electrons may be ejected from (ejected off of) the floating gate structure through the surrounding insulating oxide, and having the floating gate structure capacitively coupled to a second piece of crystalline silicon from which electrons may be injected onto the floating gate structure. The novelty of the invention resides in the utilization of avalanche injection of electrons onto and off of the floating gate using injection capacitors. This requires far less current and is more symmetric than the original dual polarity MOS analog memory devices of the prior art.

MOS analog memory with injection capacitors

A method and apparatus for characterizing the quality of an electrically thin semiconductor film and its interfaces with adjacent materials by employing a capacitor and a topside electrical contact on the same side of the electrically thin semiconductor film to thereby permit the taking of capacitance-voltage (C-V) measurements. A computer controlled C-V measuring system is operatively coupled to the contact and capacitor to modulate the potential on the capacitor. Variation of the voltage applied to the capacitor enables modulation of the potential applied to the film to thereby vary the conductivity of the film between the capacitor gate node and the topside contact.

Method and apparatus for characterizing the quality of electrically thin

Process for making semiconductor-on-insulator device interconnects

A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

Dual polarity floating gate MOS analog memory device

An integrated injection logic device formed on an insulating substrate. A lateral, load transistor and an adjacent, vertical switching transistor are formed in the semiconductor layer such that the collector region of the lateral transistor coincides with the base region of the switching transistor. The emitter of the switching transistor is located at the surface of the semiconductor injecting carriers downward into the collector. Isolated multiple collector contacts required for wired-AND logic are obtained by using separate Schottky-barrier contacts for each collector output.

Thin-film integrated injection logic

Longitudinal tensile and/or compressive strain in optical fibers is detered by an entirely optical technique. A test optical fiber optically coupled to optical injection and extraction couplers form an optically recirculating loop. A semiconductor laser diode feeds a series of narrow light pulses into the loop via the injection coupler and an oscilloscope or signal peak detector give visual indications of optical correlation when an avalanche photodiode provides responsive signals coming from the extraction coupler. Straining the optical test fiber will change the loop's length and, hence, the time delay between reoccurring pulses so that the loop frequency of the narrow optical pulses must be correspondingly changed to provide maximum signal correlation. Changing the pulse repetition rate of the laser diode until a maximum correlated signal is observed at the scope or detector provides a new resonant loop frequency that is proportional to strain. Stresses in the optical fiber due to temperature, pressure, installation, etc. can thereby be noted. Because the system employs an optical technique for measuring strain, errors which might otherwise be due to electronic time delay variations and drift are eliminated.

Fiber optical time delay resonant oscillating strain gauge

An improvement for a semiconductor laser allows the facet reflectivity to be modified to compensate for the presence of a liquid or transparent solid medium having an index of refraction n.sub.m. A first dielectric coating is disposed on an end-facet of the semiconductor laser and has an index of refraction n.sub.1. A second dielectric coating is disposed on the first dielectric coating and has an index of refraction n.sub.2. The materials of the dielectric coatings are selected such that the fraction n.sub.1 /n.sub.2 =.sqroot.n.sub.m. Thus the problems associated with reductions of laser facet reflectivity due to being in contact with a surrounding medium which optically is very different from air is overcome.

Growing community of inventors

San Diego, CA, United States of America

Graham A Garcia