Lsi Logic Corporation

Graeme M Weston-Lewis

Jackson L Ellis

David Matthew Springberg

David R Noeldner

Matthew C Muresan

Richard Martin Born

Stephen D Hanna

Steven K Stefek

The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be send. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

Command queueing engine

The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands. Automatic TE entry generation and storage to buffer memory, and automatic TE retrieval from the buffer memory and execution of entire command threads are further features provided by the present invention. As a result, bus command response latency is decreased by reducing the delay for the command to be started and at the end of the data transfer for status to be sent. Disk efficiency is increased by reducing the latency to back-fill or empty a buffer memory segment of data that will be transferred. Furthermore, the present invention is a low-cost trade-off between hardware and firmware functionality.

One retrieval channel in a data controller having staging registers and a next pointer register and programming a context of a direct memory access block

Apparatus and method for enhancing data transfer rates using transfer control blocks

System for transferring data having a generator for generating a plurality of transfer extend entries in response to a plurality of commands received

The present invention includes a method of transferring data when some of the data is masked. A mask table is provided to a storage device where it is duplicated and stored with the duplicate. The duplicate data is compared to the original data for a data protection function. A mask index counter and mask bit counter maintain provide values for specific data that are to be processed. The counters are programmable so that if a transfer error occurs, counter values for the next data after the previously transferred good data is calculated and loaded therein. The present invention also has the capability not to transfer the last requested sector if that sector is masked. The present invention evaluates whether a stop count value equals a stop threshold value when a sector is identified as being masked. The stop count value is incremented for each sector that is read from the first storage device, regardless of whether that sector is to be transferred or masked. The stop threshold value is the total number of sectors to be transferred. If the stop count value equals the stop threshold value and the sector is masked (or not), a flag is generated to stop the transfer of that last masked sector.

Hardware assisted mask read/write

A hard disk simulator that comprises a timing generator controller coupled to receive address, data and control signals; a timing generator for providing a pulse in response to signals received from the timing generator controller; and an address generator coupled to receive the control or index pulse and a programmable frequency clock to generate addresses for a hard disk simulator. The address generator includes an offset counter that generates values in response to the programmable frequency clock and the control pulse. The address generator also receives a base address that corresponds to a hard disk track. The offset counter values and the base address are combined to provide an address. The present invention also includes a method of simulating a hard disk including the step of adding an offset value to a base value to simulate rotational latency of the hard disk. The method further includes at least one of the following steps: generating the offset value from a programmable frequency clock signal that corresponds to at least two hard disk zones; resetting the offset value in response to a pulse that corresponds to a hard disk index signal; and providing base values that each correspond to respective hard disk tracks.

Hard disk rotational latency simulator

The present invention is a method to minimize the firmware overhead for multi-track transfers. To this end, the present invention provides a transfer control table. The table is used to manage sector defects or other transfer adjustments. Each entry of the table contains an affected PSA and a corresponding control instruction. The control instruction includes an action such as an interrupt/branch, take no action, skip the sector or skip the following indicated sectors. The interrupt/branch bit causes an preferably when the last sector of a track has been read or written. The table is either entirely generated at the same time or is generated to provide for a track transfer. In the latter case, the remaining table entries are generated during the platter revolution or the track seek. The method provides for minimum microprocessor intervention. To that end, the microprocessor is interrupted only at the end of the multi-track transfer.

Automated multi-track transfers

In a data processing system having few initiators or several initiators with the same parameters, support for all initiators is provided by storing sets of parameters and corresponding lists of initiator IDs in cache entries. Based on the initiator ID in a selection command, the target selects the appropriate parameters and automatically transitions to data transfer mode. Low cost support for all initiators is thus provided.

Method to store initiator information for SCSI data transfer

A storage target device controller (such as an embedded controller in a SCSI disk drive) processes multiple commands concurrently in accordance with the methods and structures of the present invention. Each command is stored within its own context within the target device controller to retain all unique parameters required for the processing of each command. Processing of multiple commands permits switching of command contexts within the target device to improve utilization of resources associated with the target device. For example, when a first, active, command context is prevented from further processing due to the status of the disk channel, an inactive command context may be swapped with the active command context to better utilize the host channel communication bandwidth. Similarly, a first active command context may be configured to automatically switch to a linked command context upon completion of processing to further ease management of multiple contexts. In a preferred embodiment of the present invention, a set of registers contain the active context while a second set of registers contains an inactive command context. The sets of registers are configured in such a way that the active and inactive context may be rapidly switched with no intervention by the microprocessor. The inactive register set may be read or written directly by the microprocessor, or may be automatically loaded/stored from/to a buffer memory in the target device by shifting a predetermined context structure into the inactive register set through an interface pad with the buffer memory.

Method and structure for switching multiple contexts in storage

A method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address. In response to a determination that the first set of data and the second set of data can be written to the disk as a single write operation, the second set of data is written to the memory as a part of the first write request. The second set of data may be automatically transferred to the memory, to be written to the storage device as a second write operation in response to a determination that the first set of data and the second set of data cannot be written as a single write operation.

Method and apparatus having automated write data transfer with optional

In a SCSI controller, unexpected messages are automatically received in response to an attention signal by receiving all of the bytes constituting the message and storing those bytes in an available register file selected from a plurality of register files in the controller. Once the entire message has been received and stored, a determination of an appropriate response is initiated. The register files are also used to hold selection information during a bus-initiated selection, so additional architecture is not required.

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Fort Collins, CO, United States of America

Graeme M Weston-Lewis