Arm Limited

Apical Limited and Arm Limited

Graeme Leslie Ingram

John Wakefield Brothers

Erik Persson

Rune Holm

Daren Croxford

Sharjeel Saeed

Michael Andrew Campbell

Peter Andrew Riocreux

David John Gwilt

Michael Jean Sole

Ian James Quinn

A method for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system is provided. The method includes obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component, predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

Memory access

The present disclosure relates generally to multi-processor arrangements and, more particularly, to a point of serialization for broadcast communications within multi-processor arrangements.

Multi-processor arrangement with point of serialization for broadcast communications

The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast regions for multi-processor arrangements.

Broadcast regions for multi-processor arrangement

The present disclosure relates generally to multi-processor arrangements and, more particularly, to broadcast hubs for multi-processor arrangements. A processing tile may comprise a broadcast hub to obtain a plurality of parameters applicable in a particular operation from at least one of a plurality of processing tiles and initiate distribution of the plurality of parameters to the plurality of processing tiles, wherein the plurality of processing tiles may execute the particular operation based at least in part on the plurality of distributed parameters.

Broadcast hub for multi-processor arrangement

The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.

Technique for operating a cache storage to cache data associated with memory addresses

A method of requesting data items from storage. The method comprising allocating each of a plurality of memory controllers a unique identifier and assigning memory transaction requests for accessing data items to a memory controller according to the unique identifiers. The data items are spatially local to one another in storage. The data items are requested from the storage via the memory controllers according to the memory transaction requests and then buffered if the data items are received out of order relative to an order in which the data items are requested.

Memory transaction request management for an ordered unit of data items

A method, processor and system for requesting data from storage. The method comprising the steps of identifying one or more characteristics of data to be fetched from storage, wherein the characteristics are predetermined; identifying a buffer size characteristic of a processor. The method also comprises the step of issuing memory requests by the processor for the data based on the identified one or more characteristics of the data and the buffer size characteristic.

Master adaptive read issuing capability based on the traffic being generated

A method for managing memory access for implementing at least one layer of a convolutional neural network is provided. The method comprises predicting an access procedure in relation to a portion of memory based on a characteristic of the convolutional neural network. In response to the prediction, the method comprises performing an operation to obtain and store a memory address translation, corresponding to the portion of memory, in storage in advance of the predicted access procedure. An apparatus is provided comprising at least one processor and storage. The apparatus is configured to predict an access procedure in relation to a portion of memory which is external to the processor. In response to the prediction, the apparatus is configured to obtain and store a memory address translation corresponding to the portion of memory in storage in advance of the predicted access procedure.

Managing memory access for convolutional neural networks

A data processing apparatus and method are provided for arbitrating between multiple access requests seeking to access a plurality of resources sharing a common access path. At least one logic element issues access requests requesting access to the resources, and each access request identifies which of the resources is to be accessed. Arbitration circuitry performs a multi-cycle arbitration operation to arbitrate between multiple access requests to be passed over the common access path, the arbitration circuitry having a plurality of pipeline stages to allow a corresponding plurality of multi-cycle arbitration operations to be in progress at any one time. Filter circuitry is provided which has a plurality of filter states, the number of filter states being dependent on the number of pipeline stages of the arbitration circuitry, and each resource being associated with one of the filter states. For a new multi-cycle arbitration operation to be performed by the arbitration circuitry, the filter circuitry selects one of the filter states that has not been selected for any other multi-cycle arbitration operation already in progress within the pipeline states of the arbitration circuitry. Then, it determines as candidate access requests for the new multi-cycle arbitration operation those access requests that are seeking to access a resource associated with the selected filter state. Such an approach allows efficient multi-cycle arbitration to take place even where the resources may have inter-access timing parameters associated therewith which prevent them from being able to receive access requests every clock cycle.

Data processing apparatus and method for performing multi-cycle arbitration

A method of controlling a memory and a memory controller are disclosed. The memory controller is operable to control a memory, the memory being operable in a plurality of modes, the memory controller comprising: memory interface logic configurable to interact with the memory in each of the plurality of modes; and memory mode change logic operable, in response to a memory mode change request instruction specifying a predetermined one the plurality of modes being issued by the memory interface logic to the memory, to request the memory interface logic to be configured to interact with the memory in the predetermined one of the plurality of modes and to prevent interaction between the memory interface logic and the memory until the memory interface logic confirms that it is configured to interact with the memory in the predetermined one of the plurality of modes. In this way, it will be appreciated that both the memory and the memory controller can be reconfigured to operate in a different mode using a single instruction which provides performance benefits, increases reliability and reduces infrastructure requirements.

Memory controller

A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests asserted by one or more of the requester elements for access to the shared resource, to perform a priority determination operation to select one of the asserted requests as a winning request. Each of the asserted requests has a priority level associated therewith, and the apparatus further comprises relative priority ordering circuitry for attributing relative priorities to the plurality of requester elements. The arbitration circuitry is responsive to the asserted requests to perform the priority determination operation in order to select as the winning request the request asserted by the requester element with the highest relative priority whose asserted request has a priority level not exceeded by any other asserted request. This provides a very flexible mechanism for performing arbitration, while allowing priority levels to be set on a request-by-request basis, thereby facilitating use of the arbitration circuitry with various quality of service mechanisms.

Data processing apparatus and method for arbitrating access to a shared resource

A self programming slave device controller is described which comprises interface circuitry and control circuitry. The interface circuitry is responsive to one or more configuration parameters to communicate data between the slave device controller and a slave device in accordance with the one or more configuration parameters. The control circuitry is responsive to one or more operating parameter signals indicative of one or more operating parameters influencing current performance characteristics of the slave device to set the one or more configuration parameters so as to control an access operation for accessing the slave device to accommodate the current performance characteristics of the slave device. In this way, an access operation can be conducted efficiently and reliably having regard to the current performance characteristics of the slave device. This makes it possible to automatically adjust configuration parameters used to control an access operation in dependence on changes to operating parameters of the slave device which may influence the performance characteristics.

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Royston, United Kingdom

Graeme Leslie Ingram