Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Graeme Barclay Boyd

Xun Cheng

Anthony Eugene Zortea

William Michael Lye

Ariel D E Sibley

Larrie Simon Carr

William Dean Warner

Hormoz Djahanshahi

Guillaume Fortin

Winston Ki-Cheong Mok

Mathieu Gagnon

Bijit Thakorbhai Patel

Matthew W McAdam

Yuriy Greshishchev

Jurgen Hissen

Kris Iniewski

Mathew McAdam

Victor Lee

David Heath Culley

Robert Sobot

The adverse effects of RF and baseband circuits are mitigated using a post-compensation method wherein a transfer function that would un-distort or complement a distorted waveform is parameterized to a relatively small number of degrees of freedom; and the parameters are estimated in a feedback loop. The error function of the feedback loop is generated by comparing some relatively low-order statistics that are known a priori or can be computed with relative certainty from the decided output waveform&#x2014;to the statistics of the corrected signal.

Adaptive signal decompression

A method to look at the incoming received data on a SerDes link while running in normal operation without requiring a second receive path or any defined or repeated data patterns to be able to generate statistical eye plots both before and after any internal equalization; generate trajectory eye plots both before and after any internal equalization; estimate TED characteristics (hence also estimate SJ jitter tolerance of the link); estimate complete Channel Impulse Response (hence also estimate the S-parameters of the complete channel); and estimate the decomposed jitter of the complete channel.

DSP-based diagnostics for monitoring a SerDes link

Large interfering signals (interferers) with spectra near a desired signal can cause distortion in a wireless receiver due to a non-linear signal path. It is typically a performance advantage to attenuate these interferers earlier in the signal path, rather than later in the signal path, because these interferers can cause saturation of amplifying stages. In certain situations, the frequency offset of an interfering signal, with respect to the desired signal, can be on the order of 10 megahertz (MHz), whereas the center frequencies can be on the order of several gigahertz (GHz). Thus, a filter with 'baseband' precision would be needed at radio frequency to notch out the interferer, which is relatively difficult to do. Disclosed is a technique to estimate the relative strength and center frequency of the interferer and to place the center frequency of a notch filter adaptively and precisely at the interferer location.

Integrated tunable RF notch filter

The invention provides an electrostatic discharge (ESD) protection device for protecting the internal circuitry of an integrated circuit chip from ESD current. The device includes a natively doped substrate having high resistance. A first well is formed in the substrate including a discharge circuit. A second well is formed in the substrate separated from the first well by the width of a natively doped region. The natively doped region has the same connectivity type and substantially the same doping profile as the substrate. During an ESD event, current leaking through the natively doped region between the discharge circuit and the second well creates a voltage that triggers the discharge circuit when reaching its trigger voltage. The resistance ratio between the natively doped region and the well is about 10 times or greater. The high resistance of the natively doped region can achieve the trigger voltage with a smaller ESD current leaking through, which decreases the size of the ESD protection device and increases its performance and sensitivity. Thus, the invention provides for more robust and cost effective ESD protection devices.

Semiconductor device for electrostatic discharge protection

Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces operate at different voltage levels than modern CMOS integrated circuits and conventional circuits to interface with these other signaling interfaces exhibit relatively high power consumption. In the context of a transmitter with a P-type substrate, an output driver is embodied in a deep N-well with retrograde P-wells and is biased with voltage biases that can float with respect to the VDD and VSS supplies provided to the CMOS integrated circuit. In the context of a receiver with a P-type substrate, a portion of a receiver is embodied in a deep N-well and biased with floating voltage biases such that the receiver is compatible with signaling received from a signaling technology with disparate voltage levels.

Input/output interfacing with low power

Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.

Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region

A method and apparatus are provided for reducing, and preferably substantially eliminating, data-pattern autocorrelations found in digital communication systems. The method employed is referred to as Data Subset Selection (DSS) and is implemented in the form of DSS engine. Autocorrelations in the data-pattern can cause many digital adaptive systems to converge to an incorrect solution. For example, the LMS method, which is often used in adaptive filtering applications, can converge to an incorrect set of filter coefficients in the presence of data-pattern autocorrelations. Digital timing recovery methods are also susceptible. Other impairments that result from data-pattern autocorrelations include increased convergence time and increased steady-state chatter. DSS reduces, and preferably substantially eliminates, data-pattern autocorrelations by selecting a subset of the data stream that either demonstrates smaller autocorrelations or no autocorrelations, thus improving the performance of the aforementioned digital adaptive systems.

Data subset selection algorithm for reducing data-pattern autocorrelations

A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.

Semiconductor device for latch-up prevention

A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both polarities and is able to tolerate a positive/negative voltage that is higher than the maximum voltage allowed for the given fabrication process. It can be used to protect an I/O pin that can be exposed to a relatively wide signal swing range.

Systems and methods for ESD protection

Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions

Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

Systems and methods for reducing frequency-offset induced jitter

A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Phase detector customized for clock synthesis unit

An apparatus and method for restoring digital pulses within a data transmission system which have degraded due to the attenuation and distortion inherent in a data transmission medium. The apparatus comprises an adaptive equalizer which receives signals from the data transmission medium, while the method by which the digital pulses are restored comprises: storing plural equalizer transfer function control values in a memory, passing the signal through an equalizer having a controllable transfer function, comparing a characteristic of the output signal of the equalizer with a reference signal and producing a difference signal, using the difference signal to select a set of stored transfer function control values from the memory, controlling the equalizer from the selected transfer function control values so as to minimize their difference from the reference signal. This apparatus and method are suitable for high-speed applications such as T1 and E1, requiring minimal configuration by the user.

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Vancouver, Canada

Graeme Barclay Boyd