Harris Corporation

Durel Corporation

Grady M Wood

Ronald G Neale

Brian Jeffrey Buell

Raymond B Patterson, Iii

A driver for an EL lamp includes a voltage detector coupled to the lamp for monitoring the voltage across the lamp and providing an indication of when the lamp is substantially discharged.

EL driver with lamp discharge monitor

A circuit for repeatedly switching current through an inductor for driving an electroluminescent lamp at alternating voltage levels having both peak positive and peak negative polarities. This circuit includes a circuit path having two zener diodes in series connection with the lamp. These zener diodes each have an anode and a cathode, and a breakdown voltage, and may have either their anodes, or cathodes connected together. These zener diodes cause conduction along the circuit path in a first direction when a positive voltage driving the lamp exceeds the breakdown voltage of a first of the two zener diodes to provide a peak detection signal representing that the lamp has reached the peak positive polarity voltage level. Further, these zener diodes cause conduction along the circuit path in a direction opposite the first direction when a negative voltage driving the lamp exceeds the breakdown voltage of a second of the two zener diodes to provide a peak detection signal representing that the lamp has reached the peak negative polarity voltage level. The circuit has a polarity control circuit coupled to the circuit path. This control circuit switches the polarity of the voltage driving the lamp to a negative polarity in response to the positive peak detection signal and switches the polarity of the voltage to the lamp to a positive polarity in response to the negative peak detection signal.

Circuit for driving an electroluminescent lamp

In a switching inverter where switches are controlled so as to provide current through an inductor which is connected in series with other switches across a battery so as to power a capacitive load, such as an electroluminescent lamp, with higher voltage than the battery voltage, the other switches, which may be SCRs, provide a path for current which charges and discharges the lamp to provide the higher voltage as an alternating voltage across the load. These other switches are switched on in synchronism with pulses of current which are produced in the inductor by circuits providing capacitances at the triggering terminals of the other switches (control electrodes or gates in the case of SCRs). These circuits are connected to the inductor so that transients or spikes, occurring when the current through the conductor is switched, enable triggering current flow with respect to the capacitances. This triggering current flow automatically triggers the other switching devices. Then, charging and discharging current paths to the load are established through these devices so as to enable the higher AC voltage to be developed across the load. The efficiency of the inverter may be increased by directing the discharge current from the load, in part, through the battery thereby recovering some of the battery energy during the discharge half cycle of the inverter. A resistor in the circuit for the triggering current provides a bias voltage which causes devices in the circuit which switches current through the inductor to pass a portion of the discharge current from the load to the battery.

Battery operated inverter circuit for capacitive loads such as

An electroluminescent lamp driver system for driving or powering an electroluminescent lamp to illuminate the display in an electronic watch, such as a quartz analog watch, uses the counter in a CMOS timekeeping chip which counts down the quartz oscillator frequency to one Hz for an analog quartz watch. The counter provides a plurality of pulse trains which are combined in digital logic to provide switching signals. The digital logic is included in the timekeeping chip and is implemented in low voltage bulk CMOS. A high voltage is required to drive the lamp and it is provided in a separate chip containing a high voltage inverter in which current is switch through an inductor in response to the switching signals from the timekeeping chip. The efficiency of the inverter is improved by generating, in the timekeeping chip, switching signals in the form of pulse trains which are asymmetric and have a duty cycle of greater than 50% to operate the switch when the output voltage from the bridge is in one-half of the AC output voltage across the lamp (the capacitance of the lamp is being charged) and has a duty cycle of less than 50% during the second half of the AC cycle when the capacitance of the lamp is being discharged. The system architecture segregates the high voltage and low voltage circuitry, eliminates redundant elements (a separate low frequency oscillator) and the digital logic for providing the pulse trains which produce switching in the inverter is located in the timekeeping chip where it may be implemented at lower cost than in the high voltage inverter chip.

Electroluminescent lamp driver system

In a switching inverter where transistor switches are controlled so as to provide current through an inductor which is connected in series with the switches across a battery so as to power a capacitive load (such as an electroluminescent lamp) with higher voltage than the battery voltage, control current for the switches and particularly the emitter to base current therethrough is shared by connecting the bases of these transistors via a current limiting resistor. Using the same base current reduces the battery drain and improves the efficiency (power applied to the load versus battery power drawn) of the inverter.

Efficient battery operated inverter circuit for capacitive loads such as

A band-gap reference having a differential amplifier with first and second inputs and an output, and a voltage divider coupled to the differential amplifier output. A first transistor having a base, emitter and collector, has its base coupled to the voltage divider, the first transistor having an emitter current density of x. A second transistor having a base, emitter and collector, has its base coupled to the voltage divider, the second transistor having an emitter current density of nx, where n is fixed. A third transistor having a base, emitter and collector, has its base coupled to the emitter of the first transistor, and its collector coupled to the first input of the differential amplifier. A fourth transistor having a base, emitter and collector, has its base coupled to the emitter of the second transistor, and its collector coupled to the second input of the differential amplifier, and the emitter of the fourth transistor being coupled to the emitter of the third transistor. The threshold voltage term for the band-gap reference is derived by setting the emitter current density for the input transistors of the differential amplifier at a fixed ratio, so that there is only one stable operating point, thereby eliminating the need for additional start-up circuitry and allowing the band-gap reference to be used in transient radiation environments.

Band-gap reference

A single input/multiple output NOR gate employs a reference voltage source for establishing the operational level of a multiple output current logic driver transistor. As the reference voltage source, the forward base-emitter voltage V.sub.be of a second transistor is used. Coupled between the current logic driver transistor and the second transistor is a multiple emitter diode-connected input transistor. One of the emitters of the input transistor is coupled in the current flow path from the current logic driver transistor to a current control resistor that is coupled in parallel with the base-emitter junction of the reference transistor, while a second emitter of the input transistor is coupled to the collector-emitter current flow path of the second (reference) transistor. In the absence of the application of current to the input transistor, the voltage level at the input is effectively equal to the sum of the forward base-emitter voltage drops of the input and second transistors. In response to the application of current to the input transistor excess input current is diverted via the second emitter of the multiple emitter input transistor and the collector-emitter path of the second transistor. Yet, because the voltage level at the input remains defined in accordance with the sum of the base-emitter voltage (V.sub.be) drops across the series connection of the base-emitter junctions of the input and second transistors, the voltage level at the input is substantially unchanged (or minimized).

Single input/multiple output logic interface circuit having minimized

A TTL gate for driving large capacitive loads with minimal current drain of the gate's power supply during the logic low output level is provided. The current drain from the power supply is minimized by a feedback means which becomes active when the logic low output level is reached. The feedback means comprises a current mirror circuit connected between the drive means and the output means of the gate. The drive means also comprises a current mirror circuit.

Power efficient TTL buffer for driving large capacitive loads

The first fire voltage of amorphous memory devices are reduced by forming the storage element of two layers, the first being in the crystalline state and the second being the amorphous state. The process deposits a first layer of switchable material and raises the temperature to crystallize the first layer. The wafer is then cooled and the remainder of the switchable material to form the storage element is deposited in an amorphous state.

Method of fabricating amorphous memory devices of reduced first fire

A current source having two current paths connected as current mirrors with an amorphous material device in one of the current paths which is electrically alterable from a high impedance state to lower high impedance states without switching to a low impedance state. A diode interconnects the amorphous material element to the current path to prevent damage to the current path during electrical alteration of the amorphous material device. The current source is included in a differential amplifier and operational amplifier to provide fine incremental trim or offset adjustment.

Adjustable current source

The Write/Erase lifetime of amorphous memory devices are extended by applying an erase pulse sequence having a first plurality of reset voltage pulses having a maximum amplitude less than the maximum threshold of the device to produce first amplitude current pulses and a second plurality of reset voltage pulses having a maximum amplitude greater than the maximum threshold to produce second amplitude current pulses having an amplitude substantially less than said current pulses. Constant current sources apply the two current pulses when the device threshold is below the maximum voltage amplitude of the first reset voltage pulses and only the second amplitude current pulses when the device threshold exceeds the maximum voltage amplitude of the first reset voltage pulses.

Multilevel sequence of erase pulses for amorphous memory devices

The Write/Erase lifetimes of amorphous memory devices are extended by applying a multilevel erase pulse wherein the first stage has a current amplitude sufficient to heat the crystal filament to the phase change temperature but not to provide the energy for the phase change and erasure of the crystal structure and the second stage has a current amplitude sufficient to heat the filament to remove the crystal structure. Preferably the first stage current is equal to the write current and the second stage is equal to the write current times the ratio of the electrical conductivity of the amorphous conducting state to the apparent conductivity of the crystalline state.

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Melbourne, FL, United States of America

Grady M Wood