Waymo LLC

Grace Nordin

Daniel L Rosenband

A system and method for low latency and higher bandwidth communication between a central processing unit (CPU) and an accelerator is disclosed. When the CPU updates a copy of data stored at a shared memory, the CPU also sends an 'invalidate' command to a cache coherent interconnect (CCI). The CCI forwards the invalidate command to a dedicated cache register (DCR). The DCR marks its copy of the data as 'out-of-date' and requests an up-to-date copy of the data from the CCI. The CCI then retrieves up-to-date data for the DCR. When the DCR receives the up-to-date data from the CCI, the DCR replaces the out-of-date data with the up-to-date data, and marks the up-to-date data with the status of &#x201c;valid.&#x201d; The DCR can then provide data to an accelerator with a status of &#x201c;out-of-date&#x201d; or &#x201c;valid.&#x201d;

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Mountain View, CA, United States of America

Grace Nordin