Cirrus Logic Inc.

Silicon Aquarius, Inc.

Gr Mohan Rao

Michael E Runas

Sudhir Sharma

Multivalued memory cell 300 includes a latch 300 having a latching node operating between a variable voltage rail and a fixed voltage rail. Circuitry 303 allows for latching of node to a voltage level of the variable voltage rail, the voltage level at the latched node representing a data value. Circuitry 303 provides for the outputing of the voltage level from the latched node.

Methods and circuits for single-memory cell multivalue data storage

A display controller 104 for use with a display device 107 operable to display images on a screen. Display controller 104 includes circuitry 201-210 for presenting first data to the display device 107 for generating an image in a first areas of the screen, the first data being retrieved from an external frame buffer 108. A display controller 104 further includes circuitry 205, 210 for presenting second data to the display device 107 for generating an image in the second area of the screen, the second data being retrieved from an internal frame buffer 206.

Display controller with integrated half frame buffer and systems and

A memory 601 comprising a plurality of static random access cell arrays 701, and a plurality of sets of latches 703 each for storing address bits associated with data stored in a corresponding one of the static random access cell arrays 701. Bit comparison circuitry 503 compares a received address bit with an address bit stored in each of the plurality of sets of latches 703 and enables access to a selected one of the static random cell arrays 701 corresponding to the set of latches 703 storing an address bit matching the received bit.

Dram with integral sram comprising a plurality of sets of address

A memory comprising a first memory bank 201 and a second memory bank 201 includes a plurality of data input/output terminals, a first subset of the plurality of data input/output terminals for accessing the first memory bank and a second subset of the plurality of data input/output terminals for accessing the second memory bank.

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Dallas, TX, United States of America

Gr Mohan Rao