United Microelectronics Corp.

Gow-Wei Sun

Pei-Jen Wang

Shu-Ya Chuang

Yann-Pyng Wu

Steven Chen

Ga-Ming Hong

A method of forming floating gates for flash memory is disclosed to improve contact properties with erase gates. The method includes formation of a tunnel oxide layer, a polysilicon layer and an interpoly insulating layer. These layers are patterned in two dry etching steps to complete floating gate definition. In the first etching step, the interpoly insulating layer is etched open in an oxide chamber to form a taper opening. The taper opening is further deepened in the second etching step, in which the polysilicon layer and the tunnel oxide layer are etched open in sequence in a poly chamber. A contact with smooth, vertical surface profile is thus formed in the second etching step. The two-step dry etching procedure is found to provide good contact profile for the floating gate to facilitate subsequent oxide deposition and contact filling. The proposed etching procedure also makes substantial operation reduction for floating gate formation and thus advantageously costs down for flash memory production.

Etching procedure for floating gate formation of a flash memory device

A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses. A second measuring step is performed to measure a third thickness loss from the first etch stop layer exposed by the monitoring opening on the wafer. The result is then compared with the correlation to deduce a fourth thickness loss from the first contact opening on the wafer.

Method of monitoring loss of silicon nitride

A method of forming a local interconnect contact opening is described. A liner layer is formed on a substrate having a gate structure, a first source/drain region, and a second source/drain region formed thereon. A planarized dielectric layer is formed over the liner layer. A photoresist layer, which defines the location of the local interconnect contact opening, is formed over the dielectric layer. A one-step etching process is performed using a C F /CO/O /Ar etching gas and the liner layer as an etching stop. The dielectric layer exposed by the opening of the photoresist layer is removed to expose the liner layer. The liner layer and the photoresist layer are removed.

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Taipei Hsien, Taiwan

Gow-Wei Sun