Broadcom Corporation

Ati International Srl

Netlogic Microsystems, Inc

Ati Technologies Inc.

Raza Microelectronics, Inc.

Govind V Malalur

Ali Alasti

Mohan V Kalkunte

Shekhar Ambe

Shiri Kadambi

Brian Hang Wai Yang

Stephen C Purcell

Korbin S Van Dyke

Gaurav Singh

Don A Van Dyke

Shalesh Thusoo

Niteen Aravind Patkar

Nguyen Nguyen

Sophia W Kao

Ngyuyen Q Nguyen

A packet duplication control system including an input port for receiving a packet and a plurality of output ports for outputting duplications of the packet is disclosed. The duplications can be suitable to support a Virtual Local Area Network (VLAN) system. The duplications can be controlled by descriptors arranged in a linked-list table. Also, the descriptors can have encoding formats, such as contiguous range encoding, non-contiguous range encoding, and discrete encoding. Further, the linked-list table can include at least one shared descriptor.

Encoding-based multicast packet duplication control suitable for VLAN systems

A method of processing DMA operations includes providing a DMA descriptor, with the DMA descriptor including a reload field therein. The DMA descriptor is then processed, and a location of a next DMA descriptor is identified based upon a condition of the reload field.

Flexible DMA descriptor support

A table lookup indexing system for the transmission of data packets in a network switch. Data is received in an input port and is divided into two parts, an index portion and a bucket portion. The index portion selects a particular bucket and the combination of the index portion and bucket portion selects a specific entry in the table.

Table lookup mechanism for address resolution

A method of constructing a lookup table for network switch includes the steps of snooping a communication channel in the network switch for lookup table information. Upon detection of lookup table information on the communication channel, the lookup table information transmitting the lookup table information to a remote system memory. This constructs a lookup table in the remote system memory.

Address resolution snoop support for CPU

A data switch for network communications includes a first data port interface and a second data port interface is provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and a common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.

Gigabit switch on chip architecture

A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs and multiplexers for receiving hash function outputs, and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.

Method and apparatus for implementing a search engine using an SRAM

A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One set of communication channels provides communication from the first and second data port interfaces to the memory management unit and the other set of communication channels provides communication from the memory management unit to the first and second data port interfaces.

A network switch includes a data port for communicating with a data network, and a statistics counter coupled to the data port for monitoring operational parameters associated with the data port. The statistics counter includes statistics registers therein. A statistics gathering circuit is connected to the statistics counter for reading the statistics registers, and for transmitting the data from the statistics registers to a remote system memory. A method of monitoring port activity in the network switch includes storing port activity data in a statistics register on a network switch, then reading the port activity data with the statistics gathering circuit. The port activity data is transmitted directly to the remote system memory, thereby reconstructing the statistics register in the remote system memory. The remote system memory can then be accessed via a remote CPU to read the reconstructed statistics register.

High-speed stats gathering in a network switch

A method of processing internal operations in a network switch includes the steps of constructing a lookup table in system memory by snooping a communication channel in a network switch for lookup table information. Upon detection of lookup table information on the communication channel, the lookup table information is transmitted to a remote system memory, thereby constructing a lookup table in the remote system memory. DMA operations are performed by providing a DMA descriptor including a reload field therein. The DMA descriptor is processed, and a location of a next DMA descriptor is identified based upon a condition of the reload field. The lookup table in remote system memory enables CPU access to the lookup table without requiring communication on the communication channel. The condition of the reload field enables flexible DMA descriptor handling. A network switch also includes elements associated with this method.

Network switch enhancements directed to processing of internal operations in the network switch

An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

Method of manufacture and apparatus of an integrated computing system

A method and apparatus for interfacing a bus with a plurality of input/output (I/O) devices includes steps for handling transactions to and from the I/O devices. Transactions from the I/O devices includes processing that begins by receiving the transactions, where each transaction is received at a rate corresponding to the providing I/O device. The processing continues by identifying, for each transaction, a corresponding section of memory for temporarily storing the transaction. The particular section of memory is identified based on the type of transaction and/or the identity of the I/O device. The processing then continues by storing each transaction in the identified section of memory when the section has an available entry. When the bus is available and a transaction has been selected, the selected transaction is provided to the bus at the rate of the bus. Processing of transactions directed towards the I/O devices includes steps for monitoring the bus during non-I/O bus intervals for transactions relating to one of the I/O devices. When a transaction is directed towards an I/O device, the transaction is interpreted to identify the particular I/O controller that supports the particular I/O device. The processing then continues by storing, at the bus rate, the transaction in the section of memory corresponding with the I/O device. Once stored in memory, the transaction is provided to an associated I/O controller, which processes the transaction at the rate of the corresponding I/O device.

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Fremont, CA, United States of America

Govind V Malalur