Vuemix, Inc.

Qlogic Corporation

Netxen, Inc.

Vyumix, Inc.

Advanced Micro Devices Corporation

Conexant Systems, Inc.

Universal Network Machines, Inc .

Govind Kizhepat

Yung-Hsiao Lai

Erik Matthew Nystrom

Suresh Kadiyala

Kenneth Y Y Choy

Omar M Kinaan

Denise Kerstein

Philip Simmons

Richard A Relph

Min H Teng

Gary A Rogan

Ronald Edward Hinchley

Vikram Karvat

Sarvesh Arun Telang

Kenneth Y Choy

Phillip Lowe

A composite video including a plurality of videos in a single stream is sent from a video streamer server to a client, where it is presented on an electronic display. A user may make a selection in the composite video that is translated to an absolute media reference that may include information identifying which video of the composite video was selected, an absolute media time identifying an elapsed time from the beginning of the video to the selection, and/or an absolute media spatial coordinate identifying a spatial location of the video that was selected. Auxiliary information related to the composite video may be obtained based on the selection and the absolute media reference and displayed to the user.

Auxiliary information data exchange within a video environment

In some embodiments, a server system composites in real-time, in response to a user video search query, a standard-compliant (e.g. MPEG-4/H.264) SD or HD video stream encoding a rectangular (x-y) composite video preview panel array (grid) of video search results. Each panel/tile in the rectangular panel array displays a temporal section (e.g. the first 90 seconds, looped-back) of a video identified in response to the user query. Generating the composite video panel array in real-time is achieved by compositing the component video panels in the compressed domain, after each panel undergoes off-line a compressed-domain pre-compositing preparation process that facilitates dynamic compositing of the panels into a single video stream. The pre-compositing preparation includes transcoding to a format having a down-scaled common resolution, common GOP structure, and one-slice-per-row slice structure.

Scalable real-time video compositing systems and methods

In some embodiments, a video (e.g. MPEG-2, H.264) transcoder channel pool is used to transcode multiple independent videos (programs) per channel substantially concurrently. A syntactically-unified combined input video stream is assembled by interleaving segments of different input video streams. The combined stream may be a container stream or elementary stream. Each segment includes one or more groups of pictures (GOP). The combined stream includes the payload video data of the input streams in unmodified form, and modified header data characterizing the combined stream as a single video stream. The combined input stream is transcoded using a single transcoder channel/input port to generate a combined output video stream. Multiple independent output video streams are assembled by de-interleaving segments of the combined output video stream according to stored interleaving break identifiers. Assembling the output video streams includes updating output video stream header fields according to stored header field data.

Video transcoder stream multiplexing systems and methods

A method and system for audio selection is disclosed. Multiple active videos are rendered in a single video stream and the multiple active videos are simultaneously displayed on a client machine. A user selects a video from among the multiple active videos for which associated audio is presented. As the user selects different videos the previous audio is stopped and the new audio is played. The new audio is synchronized to the selected video.

Audio selection from a multi-video environment

In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.

Direct hardware processing of internal data structure fields

A video streamer aggregates multiple videos into a single video stream for delivery to a client to be displayed. The multiple videos are active to allow motion of the multiple videos to be shown. The multiple videos are part of an electronic program guide. Additional information related to one or more of the videos may be obtained and displayed by the client. One of the videos may be selected to be enlarged and/or have audio from that video played.

Program selection from within a plurality of active videos

In some embodiments, a server system composites in real-time, in response to a user video search query, a standard-compliant (e.g. MPEG-4/H.264) SD or HD video stream encoding a rectangular (x-y) composite video preview panel array (grid) of video search results. Each panel/tile in the rectangular panel array displays a temporal section (e.g. the first 90 seconds, looped-back) of a video identified in response to the user query. Generating the composite video panel array in real-time is achieved by compositing the component video panels in the compressed domain, after each panel undergoes a compressed-domain pre-compositing preparation process that facilitates dynamic compositing of the panels into a single video stream. The pre-compositing preparation includes transcoding to a format having a down-scaled common resolution, common GOP structure, and one-slice-per-row slice structure.

In some embodiments, a system allowing a flexible upgrade of a computer system (e.g. server) to a high-speed network connection comprises base configuration motherboard or network card including a set of low-speed (e.g. 1 Gbps Ethernet) media access controllers (MACs) each connected to a low-speed physical controller (PHY), and a set of high-speed (e.g. 10 Gbps Ethernet) MACs. An expansion card including high-speed PHYs of choice can be connected by an end user to the base configuration motherboard or network card. A flow classifier classifies data sent/received over both high-speed and low-speed ports, and a single driver may control both high- and low-speed ports. One or both of the motherboard and/or expansion card are configured according to a detected type (e.g. physical layer standard, vendor) of expansion card connected to the motherboard and/or type of physical medium connected to the expansion card.

Flexible server network connection upgrade systems and methods

In some embodiments, a hardware linked-list manager includes a wildcard search controller for generating corresponding queue-specific read requests from wildcard read requests. The linked-list manager may be part of an on-chip interagent switch for allowing a plurality of agents to communicate with each other. The interagent switch may include a crossbar switch and a plurality of hardware linked-list managers integrated on the chip, connected to a random access memory, and connected to the crossbar switch such that the crossbar switch is capable of connecting each of the linked-list managers to each of the agents. Each linked-list manager sends agent-generated data to the memory for storage in the memory as a linked-list element, and retrieves linked-list elements from memory in response to agent read requests. A shared free-memory linked-list manager may maintain a linked list of free memory locations, and provide free memory address locations to a linked list manager upon request.

Switching systems and methods using wildcard searching

A dual-mode network storage controller integrated on a chip is connected to a first set of hosts over a block-level storage area network (SAN), and to a second set of hosts over a metadata Ethernet/IP network. The dual-mode storage controller is also connected to one or more storage devices, such as a Redundant Array of Independent Disks (RAID). The storage controller comprises dedicated-hardware metadata translation logic for translating metadata (e.g. file-level) storage commands into block-level storage commands. The storage controller can also include block translation logic for translating logical block-level storage commands into physical block-level storage commands. The storage controller further comprises multiplexing logic for sequentially transmitting to the storage device(s) block level storage commands derived from the commands received from the first set of hosts and the second set of hosts. The storage controller allows the first set of hosts and the second set of hosts to share a single storage device.

Dual-mode network storage systems and methods

In some embodiments, multiple functional blocks (agents) in a complex integrated circuit are connected to a physically-distant shared resource (e.g. a memory controller) through packet buses which do not depend on establishing clock-cycle sequenced handshakes. On-chip repeaters including one or more register stages are used to segment the agent-shared resource interconnects into multiple segments, each shorter than a single-clock-cycle pathlength. The interconnects of multiple closely-spaced agents can be routed to the shared resource through an on-chip router having a single routed connection to the shared resource, for reducing the floorplan space taken by interconnects. The packet-based communications protocols do not require redesigning the agents or memory controller to make protocol changes accounting for the clock cycles inserted by repeaters and/or routers. Each agent can include a port register for storing a corresponding port number of the shared resource, to facilitate the host-programmable assignment of agents to shared resource ports.

On-chip packet-based interconnections using repeaters/routers

A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware engine performs operations and computations on data as the data traverses paths through the functional units under control of software. The functional units include logic resources, examples of which are flip-flops, latches, arithmetic logic units, random access memory, and the like. The routing units are responsive to the software control signals that are turned on or off to steer the data through these resources. Operations and computations are accomplished according to the steering of the data through the functional units that control the functions performed.

Growing community of inventors

Los Altos Hills, CA, United States of America

Govind Kizhepat