Ceremorphic, Inc.

Redpine Signals, Inc.

Silicon Laboratories Inc.

Govardhan Mattela

Suyash Kandele

Joydeep Kumar Devnath

Ananya Shrivastava

Mohammed Sumair

Sumant Kumar Singh

Venkat Mattela

Heonchul Park

Manmohan Tripathi

Radhika Ponnamaneni

Chandrajit Pal

A computer-implemented method includes training at least a generative adversarial network, the method operable on one or more processors. The method includes at least (1) applying pattern extraction to a set of training data to extract one or more feature embeddings representing one or more features of the training data, (2) attenuating the one or more feature embeddings to create one or more attenuated feature embeddings, (3) providing the one or more attenuated embeddings to a generator of the generative adversarial network as a condition to at least partly control the generator in generating synthetic data, the providing being performed automatically and dynamically during training of the generator, and (4) with the generator, generating synthetic data based at least in part on the attenuated embeddings.

Systems and methods for a lightweight pattern-aware generative adversarial network

A first chiplet parses at least a message into ordered message blocks that are associated with index values. The first chiplet generates a substitution value by executing a pseudo-random number generator using a seed value that is computed with at least (i) a first random or pseudo-random number and at least (ii) a first message block. The first chiplet generates a sequencing value by executing a pseudo-random number generator using a seed value that is computed with at least (i) a second random or pseudo-random number and at least (ii) an index value for the first message block. The first chiplet generates a first ciphertext block with at least the substitution value and the sequencing value and further generates a second ciphertext block at least partly with the first ciphertext block. The blocks are concatenated and transmitted to a second chiplet.

PRNG-based chiplet-to-chiplet secure communication using chaining of message blocks

A system and method for a switching network is disclosed. A plurality of first switching assemblies, second switching assemblies and intermediate switching assemblies with each of the first switching assemblies, second switching assemblies and intermediate switching assemblies having at least two input ports and output ports is provided. Selective one of the two input ports is configured to receive a data to be processed and delivered at a designated one of the output ports. Received data passes through one or more selective first switching assemblies, one or more intermediate switching assemblies and one or more selective second switching assemblies, before the received data is delivered to the designated port. A plurality of additional data is received in one or more of the input ports to be delivered to one or more designated output ports is processed before the received data is delivered to the designated one of the output ports.

System and method for a pipelined multi-layer switching network

An unenrolled lightweight node is on a decentralized network with a trusted node and a plurality of peers. The unenrolled lightweight node and the peers run a lightweight blockchain consensus algorithm. The unenrolled lightweight node includes (a) circuitry for storing a token that includes a signature that includes at least a signature of at least a first identifier signed with a private key of the trusted node, the first identifier being associated with a public key of the unenrolled lightweight node, and (b) circuitry for broadcasting a request for blockchain enrollment of the unenrolled lightweight node to the plurality of peers. The authentication request including at least a second identifier that is associated with at least a public key of the unenrolled lightweight node, a signature created with at least the second identifier and a corresponding private key of the unenrolled lightweight node, and the token.

Device authentication using blockchain

A method is performed with a group of chiplets. The method includes: (1) parsing a message into at least a group of ordered message blocks associated with a group of index values, which are indicative of positions of individual message blocks relative to one another; (2) generating two or more substitution values based at least in part on execution of two or more pseudo-random number generators (PNRG's) using seeds associated with the bits of blocks of the group of message blocks; (3) generating two or more sequencing values based at least in part on execution of two or more PNRG's using seeds associated with index values of the group of index values; (4) generating a group of ciphertext blocks at least in part with XOR operations using at least the substitution values and the sequencing values; (5) concatenating the group of ciphertext blocks; and (6) transmitting.

PRNG-based chiplet to chiplet secure communication using counter resynchronization

A cryptographic method includes (1) with the first chiplet, parsing a message into one or more message blocks (2) dynamically generating a first target value that is associated with a first key (3) dynamically generating a second target value that is associated with a second key (4) encrypting at least one message block of the at least one or more message blocks to generate some ciphertext, the encryption being performed with at least one operation that includes at least one XOR operation, the at least one XOR operation performed at least in part with the first target value and with at least the second target value, the first target value and the second target value being accessed via the first and second keys, respectively; and (5) with at least one processing device associated with the first chiplet, transmitting the some ciphertext to a second chiplet.

Look up table (LUT) based chiplet to chiplet secure communication

A multi-stage processor has a pre-fetch stage, and a sequence of pipelined processor stages. A thread map register contains thread identifiers, and a thread map valid register has locations corresponding to the thread map register and indicating whether a value in the thread map register is to be fetched or not, and a thread map length register indicates the number of thread map register locations forming a canonical sequence of thread identifiers to the pre-fetch stage. The pre-fetch stage does not act on a thread identifier with a not valid thread map valid value, thereby saving power in low demand conditions.

Multi-threaded processor with power granularity and thread granularity

A lightweight node in a decentralized network includes stores a blockchain with a plurality of blocks. The lightweight node adds blocks to the blockchain successively. A given block having a header and a body. The header includes a data merkle root generated as a root hash of a data merkle tree with one or more leaf nodes that are one or more hashes. A given hash being a hash of a combination of (1) a public key associated with a lightweight node of the decentralized network and (2) of a validity value associated with the public key indicating whether the public key is a valid public key. The data merkle root being insufficient for restoring the data merkle tree. But with a public key and an intermediate hash the date merkle root is sufficient for at least partly verifying the public key.

Efficient storage of blockchain in embedded device

A system for transmission of incident information includes maintaining a table of RSSI values for a plurality of stations. When an incident is detected, the system first sends a broadcast packet with incident information, and next sends a unicast packet to any station below a particular RSSI threshold until the unicast packet is acknowledged or a retransmission interval passes.

Device for a vehicular network providing incident retransmission

Incident broadcast retransmission in a vehicular network

A multi-protocol transceiver provides a plurality of RF front ends, each responsive to a particular protocol and frequency, a common set of analog/digital converters, a baseband processor which receives and demodulates and also modulates and transmits baseband wireless packets for mixing to a carrier frequency by each RF front end. A timing controller allocates intervals of time for a first protocol such as WAVE protocol, and also allocates exclusive intervals of time for a second protocol such as Bluetooth.

Growing community of inventors

Hyderabad Telangana, India

Govardhan Mattela