Imec Vzw

Imec

Katholieke Universiteit Leuven

Vrije Universiteit Brussel

Gouri Sankar Kar

Mihaela Ioana Popovici

Antonino Cacciato

Johan Swerts

Ludovic Goux

Stefan Cosemans

Sebastien Couet

Davide Francesco Crotti

Jan F Van Houdt

Amey Mahadev Walke

Dirk Wouters

Geoffrey Pourtois

Pieter Blomme

Trong Huynh Bao

Hanns Christoph Adelmann

Koen Martens

Sandip Halder

Min-Soo Kim

Hendrik F W Dekkers

Romain Delhougne

Manu Komalan Perumkunnil

Sushil Sakhare

Kevin Garello

Victor M Blanco

Van Dai Nguyen

Bappaditya Dey

Antonio Cacciato

Jose Diogo Costa

Luca Di Piazza

Jürgen Bömmels

Jasper Bizindavyi

Michiel Jan Van Setten

Siddharth Rao

Senthil Srinivasan Shanmugam Vadakupudhu Palayam

Yueh Chang Wu

Woojin Kim

Bart Vermeulen

Karl Opsomer

Viktor M Blanco

Hendrik FW Dekkers

Kim Min-Soo

Example embodiments relate to ferroelectric devices. An example ferroelectric device layer structure includes a first electrode. The ferroelectric device layer structure also includes a second electrode. Additionally, the ferroelectric device layer structure includes a ferroelectric layer of hafnium zirconate (HZO). Further, the ferroelectric device layer structure includes an oxide layer of NbOor TaOarranged on the ferroelectric layer. The ferroelectric layer and the oxide layer are arranged between the first electrode and the second electrode.

Ferroelectric device

A method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device is disclosed. The MTJ device is switchable between a first resistance state and a second resistance state. A first threshold voltage for switching the MTJ device from the second resistance state to the first resistance state is lower than a second threshold voltage for switching the MTJ device from the first resistance state to the second resistance state. The method includes applying a first voltage pulse across the MTJ device with an amplitude having an absolute value equal to or greater than the first threshold voltage and lower than the second threshold voltage, thereby setting the MTJ device to the first resistance state regardless of whether the MTJ device initially is in the first or second resistance state.

Memory device and method of operating a voltage-controlled magnetic anisotropy (VCMA) magnetic tunnel junction (MTJ) device

In an aspect, a mixed metal oxide comprises or consists essentially of: a mixture comprises or consisting essentially of 0.30 to 0.69 parts by mole Mg, 0.20 to 0.69 parts by mole Zn, 0.01 to 0.30 parts by mole of a third element selected from Al and Ga, and, either, when the third element is Al, 0.00 to 0.31 parts by mole of other elements selected from metals and metalloids, or, when the third element is Ga, 0.00 to 0.15 parts by mole of other elements selected from metals and metalloids, wherein the sum of all parts by mole of Mg, Zn, the third element, and the other elements amounts to 1.00, wherein the amount in parts by mole of the other elements is lower than the amount in parts by mole of Mg and is lower than the amount in parts by mole of Zn; oxygen; and less than 0.01 parts by mole of non-metallic and non-metalloid impurities.

Mixed metal oxide

The disclosed technology relates to a magnetic domain wall-based memory device including a combination of at least one magnetic domain wall track and at least one spin orbit torque (SOT) track, which are arranged in a crossing architecture. The SOT track can include a first strip of a patterned SOT generating layer, wherein the first strip extends into a first direction and is configured to pass a first current along the first direction. The magnetic domain wall track can include a second strip of the patterned SOT generating layer and a first magnetic strip of a patterned magnetic free layer, wherein the second strip extends along a second direction and intersects with the first strip in a first crossing region. The first magnetic strip can be provided on the second strip including the first crossing region and can be configured to pass a second current along the second direction. Further, a first and a second MTJ structure can be provided on the first magnetic strip and can be separated in the second direction. The first MTJ structure can be provided above the first crossing region and can be provided with a first voltage gate.

Magnetic domain wall-based memory device with track-crossing architecture

The disclosure relates generally to image processing. For example, the invention relates to a method and a device for de-noising an electron microscope (EM) image. The method includes the act of selecting a patch of the EM image, wherein the patch comprises a plurality of pixels, wherein the following acts are performed on the patch: i) replacing the value of one pixel, for example of a center pixel, of the patch with the value of a different, for example randomly selected, pixel from the same EM image; ii) determining a de-noised value for the one pixel based on the values of the other pixels in the patch; and iii) replacing the value of the one pixel with the determined de-noised value.

Method for de-noising an electron microscope image

The present disclosure relates to magnetic devices. In particular, the disclosure relates to magnetic memory and logic devices that employ the voltage control of magnetic anisotropy (VCMA) effect for magnetization switching. The present disclosure provides a method for manufacturing a magnetic structure for such a magnetic device. The method comprising the following steps: providing a bottom electrode layer, forming a SrTiO(STO) stack on the bottom electrode layer by atomic layer deposition (ALD) of at least two different STO nanolaminates, forming a magnetic layer on the STO stack, and forming a perpendicular magnetic anisotropy (PMA) promoting layer on the magnetic layer, the PMA promoting layer being configured to promote PMA in the magnetic layer.

Magnetic structure for magnetic device

According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

Spin-torque transfer switchable magnetic tunnel junction unit and a memory device

The disclosed technology generally relates to magnetic devices and more particularly to magnetic tunnel junction (MTJ) devices in which switching can be mediated by spin-orbit torque, and further relates to a method of fabricating such devices. In an aspect, a magnetic tunnel junction (MTJ) device includes a spin-orbit torque (SOT) mediating layer, a hard-mask layer used to define a shape of the SOT layer, a magnetic tunnel junction arranged between the SOT layer and the hard-mask layer. The MTJ includes at least a free layer and a reference layer separated by a non-magnetic barrier layer. The device further includes at least two electrical accesses arranged to contact the SOT layer to pass a write current therethrough. To provide field-free switching of the free layer, the device further includes a ferromagnetic element as at least one of a ferromagnetic sublayer of the hard-mask and a material in the electrical accesses.

Spin-orbit torque magnetic tunnel junction device and method of fabricating same

The disclosed technology relates to a structure for use in a metal-insulator-metal capacitor. In one aspect, the structure comprises a bottom electrode formed of a Ru layer. The Ru layer has a top surface characterized by a grazing incidence X-ray diffraction spectrum comprising a first intensity and a second intensity, the first intensity corresponding to a diffracting plane of Miller indices (0 0 2) being larger than the second intensity corresponding to a diffracting plane of Miller indices (1 0 1). The structure further comprises an interlayer on the top surface of the Ru layer, the interlayer being formed of an oxide of Sr and Ru having a cubic lattice structure, and a dielectric layer on the interlayer, the dielectric layer being formed of an oxide of Sr and Ti.

Structure for use in a metal-insulator-metal capacitor

A magnetic tunnel junction memory device is disclosed. In one aspect, the memory device comprises a substrate, a first memory element, and a second memory element, wherein the first memory element and the second memory element are formed of a stack comprising at least a first layer and a second layer, the first layer being arranged between the substrate and the second layer. The memory device further comprises a first selector device arranged to contact the first memory element, and a second selector device arranged to contact the second memory element, wherein the first selector device and the second selector device are arranged in or above the second layer. The first memory element and the second memory element are interconnected via the first layer, and are separated from each other by a trench formed in the second layer.

Method for manufacturing a magnetic tunnel junction device and device manufactured using such method

In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

Three-dimensional semiconductor device and method of fabricating same

The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices comprising a magnetic tunnel junction (MTJ). In an aspect, a method of forming a magnetoresistive random access memory (MRAM) includes forming a layer stack above a substrate, where the layer stack includes a ferromagnetic reference layer, a tunnel barrier layer and a ferromagnetic free layer and a spin-orbit-torque (SOT)-generating layer. The method additionally includes, subsequent to forming the layer stack, patterning the layer stack to form a MTJ pillar.

Magnetic random access memory device having magnetic tunnel junction

The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (MTJ), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. A magnetic tunnel junction (MTJ) device is formed in the first dielectric layer and in the second metallization layer and electrically connected to a first metallization layer and the third metallization layer.

Semiconductor device with integrated magnetic tunnel junction

A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer. By performing a plurality of processing steps on the repetitive sequence a three-dimensional resistive memory array is obtained. A three-dimensional resistive memory array is further disclosed.

Three-dimensional resistive memory array

Described herein is a method for forming a vertical memory device () having a vertical channel region () sandwiched between a source region () and a drain region (). A charge trapping layer () is provided either side of the vertical channel region () and associated source and drain regions (). The source region () comprises a junction between a first region () comprising a first doping type with a first doping concentration and a second region () comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region () comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.

Vertical memory device and method for making thereof

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Leuven, Belgium

Gouri Sankar Kar