Yozan Corporation

Sharp Kabushiki Kaisha Corporation

Gouliang Shou

Makoto Yamamoto

Sunao Takatori

Kazunori Motohashi

Takashi Tomatsu

An stable inverted amplifying circuit includes an odd number of CMOS inverters and a feedback capacitance. Balancing resistances decrease the inverter open gain and limit the gain of the entire circuit. Serial capacitances act to prevent low-frequency oscillation. Oscillation-preventing circuits are also provided to reduce high-frequency oscillation. Sleep, refresh, and sleep-refresh switches are used to cancel residual loads and reduce power consumption.

Inverted amplifying circuit

Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X.sub.i corresponding to each element of the first input data string is input to capacitance switching circuits 10.sub.1 to 10.sub.n through input terminals 1.sub.1 to 1.sub.n. m bit of digital control data A.sub.i corresponding to each element of the second input data string are input to each capacitance switching circuit 10.sub.i, and each bit a.sub.j of the control signal A.sub.j is input to the corresponding multiplexer circuit 6.sub.ij. In the multiplexer circuit 6.sub.ij, the capacitances C.sub.ij corresponding to the value of each bit of the control signal a.sub.j are connected to the input terminal 1.sub.i or the reference charge V.sub.STD. The voltages corresponding to the products of inputted analog voltages X.sub.1 and the control signals A.sub.i are outputted from each capacitance switching circuit 10.sub.j. The output voltages of each capacitance switching circuit 10.sub.i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

Multiplication circuit

A signal integration circuit having a first MOSFET including a drain connected to a power source and a gate connected to a plural number of the first capacitances in parallel; and an input means connected to each capacitance; in which each input means comprises; the second MOSFET whose source is connected to the first capacitance through a resistance, which receives an input pulse signal, and whose gate is grounded through the second capacitance, and the third MOSFET whose source is connected to a gate of the second MOSFET, whose drain is connected to a power source, and whose gate receives a pulse signal for setting weight; a gate of the first MOSFET receiving a reference saw-tooth signal, a source of the first MOSFET grounded through the third capacitance, and an output pulse signal being output from this source of said first MOSFET.

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