Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Gou Fukano

Tomoaki Yabe

Nobuaki Otsuka

Keiichi Kushida

A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Nonvolatile semiconductor memory device with a plurality of memory blocks and a shared block decoder

Nonvolatile semiconductor memory device with a plurality of memory blocks with memory strings and a shared block decoder to allow the number of selection signals to be reduced

Nonvolatile semiconductor memory device including at least one memory block and allowing the number of selection signals to be reduced

Nonvolatile semiconductor memory device with block decoder

Nonvolatile semiconductor memory device

According to one embodiment, a semiconductor storage device includes memory cells including serially-connected variable-resistance layer and diode. A memory cell array includes the memory cells arranged on a plane including a first and second axes and has a first region lying along an edge of the array and a second region lying opposite to the edge with respect to the first region. A first wiring is continuous along the first axis between both ends of the array, partly lies in the second region, and is connected to the first ends of the memory cells. A second wiring lies along the first axis only in the first region, is connected to the first ends of the memory cells, and is divided between adjacent memory cells. A third wiring is continuous along the second axis between both ends of the array, and connected to the second ends of the memory cells.

Semiconductor storage device

According to one embodiment, a resistance change memory includes a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2, and a first to a n-th drivers which drives the first to the (n+1)-th conductive lines. The odd-numbered conductive lines are extends in a first direction along a surface of the semiconductor substrate. The even-numbered conductive lines are extends in a second direction along the surface of the semiconductor substrate. Sizes of the first to (n+1)-th drivers become large gradually from the first driver to the (n+1)-th driver.

Resistance change memory

A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell.

Semiconductor memory device

This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

Growing community of inventors

Tokyo, Japan

Gou Fukano