International Business Machines Corporation

Gottfried Ungerbock

Giovanni Cherubini

Pierre R Chevillat

Dietrich G Maiwald

Philippe Emmanuel Thirion

Sedat Oelcedillaer

Hans-Peter Kaser

Hans P Kaser

Adaptive equalization for PRIV transmission systems

The start-up time for typical current generation modems for full-duplex data transmission over the Public Switched Telephone Network (PSTN) as specified in CCITT Recommendations V.32 and V.32bis is about 4 to 8 seconds. This invention reduces that start-up time to about 0.5 to 1 second by applying interleaved and overlapping sending and receiving operations of two connected modems, the calling modem and the answering modem. Both modems send and receive simultaneously in a predetermined sequence at different frequency ranges, channel probing tones (e.g. for evaluating the channel bandwidth), repetitive identification messages (e.g. for determining reference times, identifying modulation rates and center frequencies), repetitive response messages (e.g. for transmitting the determined bandwidths and reference times to the other modem and determining round-trip delays), and training sequences (e.g. for determining echoes, frequency shifts, and receiver settings). The modems then transmit data in a full-duplex mode at the modulation rate and center frequency appropriate for the channel and at an initial bit rate. The maximum achievable bit rate may be achieved later during the full-duplex transmission through rate negotiations.

Full-duplex start-up for modems

In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.

Arithmetic device for concurrently summing two series of products from

In a receiver for PSK modulated signals, carrier phase tracking is achieved by a feedback loop comprising a phase error predictor. Means are provided for adaptively setting the gain factor in the phase error predictor to an optimum value, in response to successive residual phase errors.

Arrangement for compensating carrier phase errors in a receiver for

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Langnau am Albis, Switzerland

Gottfried Ungerbock